公开(公告)号：DE102004020593A1

公开(公告)日：2005-11-24

申请号：DE102004020593

申请日：2004-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LUYKEN R JOHANNES ,  LANDGRAF ERHARD

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092 ,  H01L21/336

Abstract: A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.

公开(公告)号：DE10241172A1

公开(公告)日：2004-03-18

申请号：DE10241172

申请日：2002-09-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  HOFMANN FRANZ ,  SPECHT MICHAEL ,  LANDGRAF ERHARD ,  LYKEN R JOHANNES

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  H01L21/8247

Abstract: The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

公开(公告)号：DE10220923A1

公开(公告)日：2003-11-27

申请号：DE10220923

申请日：2002-05-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPECHT MICHAEL ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  ROESNER WOLFGANG ,  STAEDELE MARTIN

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788

公开(公告)号：DE19957303A1

公开(公告)日：2001-06-07

申请号：DE19957303

申请日：1999-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  HOFMANN FRANZ

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/78

Abstract: According to the invention, a recess (V) is interposed between a first source/drain region (S/D1) and a second source/drain region (S/D2) that reach down to a first depth (T1), said recess reaching deeper than the first depth (T1). The recess (V) is provided with a gate dielectric (GD). A gate electrode (GA) is disposed in the recess (V) and extends from the bottom of said recess (V) down to the first depth (T1). An insulating structure (I) is disposed on said gate electrode (GA) and spaces a contact (K) to the gate electrode (GA) in the recess (V) apart from the source/drain regions (S/D1, S/D2). Said source/drain regions (S/D1, S/D2) can be subdivided into highly doped regions (H1, H2) and lightly doped regions (N1, N2). In order to produce self-adjusting source/drain regions (S/D1, S/D2) with respect to the gate electrode (GA) at least parts of the source/drain regions (S/D1, S/D2) are produced by oblique implantation after the gate electrode (GA) has been produced and before the insulating structure (I) and the contact (K) are produced.