公开(公告)号：DE10216838A1

公开(公告)日：2003-11-06

申请号：DE10216838

申请日：2002-04-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SPECHT MICHAEL ,  HOFMANN FRANZ ,  STAEDELE MARTIN ,  ROESNER WOLFGANG ,  LUYKEN R JOHANNES

IPC: H01L21/762 ,  H01L29/78 ,  H01L21/336

Abstract: The substrate (600) has a carrier layer (501), a silicon oxide insulating layer (502) applied to the carrier layer with at least two regions of different thicknesses so that a stepped insulating layer surface is formed and an at least partly epitaxially formed silicon semiconducting layer (303) formed on the stepped surface with a planar surface opposite the stepped surface. AN Independent claim is also included for the following: a method of manufacturing and inventive device.

公开(公告)号：DE10203998A1

公开(公告)日：2003-08-21

申请号：DE10203998

申请日：2002-02-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LANDGRAF ERHARD ,  SELL BERNHARD ,  HOFMANN FRANZ ,  LUYKEN R JOHANNES ,  GOLDBACH MATTHIAS

IPC: B81C1/00 ,  H01L21/28 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L21/336 ,  H01L21/8247

Abstract: Production of a toothed structure in a crystal structure in or on a substrate (100) comprises forming trenches (102, 202) using a mask on the substrate and an etching process, and etching the unmasked region of the substrate having at least one trench to form the toothed structure. Independent claims are also included for: method for producing a floating gate transistor; and floating gate transistor. Preferred Features: The crystal structure contains silicon. The structured surface of the crystal structure in the substrate has a (100) crystal orientation according to the Miller Indices. The trench is trapezoidal or V-shaped. A silicon dioxide layer is applied to the toothed structure.

公开(公告)号：DE10250829B4

公开(公告)日：2006-11-02

申请号：DE10250829

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  SPECHT MICHAEL ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ

IPC: H01L27/115 ,  G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/12 ,  H01L27/28 ,  H01L29/788 ,  H01L29/792 ,  H01L51/00 ,  H01L51/30

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

公开(公告)号：DE10227605A1

公开(公告)日：2004-01-15

申请号：DE10227605

申请日：2002-06-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  KRETZ JOHANNES

IPC: H01L21/8242 ,  H01L25/065 ,  H01L21/58 ,  H01L21/283 ,  H01L27/108 ,  H01L27/112

Abstract: A layer system comprises a substrate having a surface processed with a conductive metal structure and an opposite processed second surface. A second substrate is attached by a third surface to the first surface of the first substrate. An independent claim is also included for a process for producing the system above.

公开(公告)号：DE102004020593A1

公开(公告)日：2005-11-24

申请号：DE102004020593

申请日：2004-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LUYKEN R JOHANNES ,  LANDGRAF ERHARD

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L27/092 ,  H01L21/336

Abstract: A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.

公开(公告)号：DE10337830A1

公开(公告)日：2005-04-07

申请号：DE10337830

申请日：2003-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUTTKOWSKI EIKE ,  ILICALI GUERKAN ,  LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  ALBA MANUELA

IPC: B81C1/00 ,  H01L21/768 ,  H01L21/283 ,  G01N13/10 ,  H01L51/10

Abstract: Producing a multiple layer arrangement with a metal layer comprising applying a metal layer on one surface of a first wafer, applying an intermediate layer on the metal layer, applying a second wafer on the intermediate layer, and removing the first wafer so that the metal layer is exposed, is new.

公开(公告)号：DE102005031517A1

公开(公告)日：2007-02-01

申请号：DE102005031517

申请日：2005-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUTTKOWSKI EIKE ,  LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  ROESNER WOLFGANG

IPC: H01L27/24 ,  H01L49/00

Abstract: An electronic component has a substrate with at least one insulating layer on the substrate, a trench in the insulating layer, a first electrode mounted in the region of the trench and second electrode, gap (304) between the first electrode and second electrode and a molecular film (305) in the gap (304). Independent claims are included for the following. (1) an arrangement of electronic components; and (2) the production of an electronic component.

公开(公告)号：DE10250829A1

公开(公告)日：2004-05-19

申请号：DE10250829

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  SPECHT MICHAEL ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  GRAHAM ANDREW

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L27/28 ,  H01L29/788 ,  H01L29/792 ,  H01L51/00 ,  H01L51/30

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.

公开(公告)号：DE10122659A1

公开(公告)日：2002-12-05

申请号：DE10122659

申请日：2001-05-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  LUYKEN R JOHANNES ,  FREY ALEXANDER

IPC: C12Q1/00 ,  G01N33/543 ,  G01N33/50 ,  G01N33/68 ,  C12Q1/68

Abstract: The biochip comprises a substrate, at least one sensor, arranged on or in the substrate and an electrically conducting permeation layer, arranged at a given, non-zero separation from the surface of the substrate, to which an electrical voltage may be applied. The biochip arrangement may be used, for example, as a DNA sensor, whereby a receptor molecule, immobilised on the sensor electrode, hybridises a DNA molecule and thus an electrical sensor signal which may be drawn from between sensor electrodes, is influenced in a characteristic manner.

公开(公告)号：DE10337830B4

公开(公告)日：2005-08-25

申请号：DE10337830

申请日：2003-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUTTKOWSKI EIKE ,  ILICALI GUERKAN ,  LUYKEN R JOHANNES ,  HOFMANN FRANZ ,  ALBA MANUELA

IPC: B81C1/00 ,  H01L21/768 ,  H01L21/283 ,  G01N13/10 ,  H01L51/10