公开(公告)号：DE10054520C1

公开(公告)日：2002-03-21

申请号：DE10054520

申请日：2000-11-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  MUELLER GERHARD

IPC: G11C11/14 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/00 ,  G11C8/12 ,  G11C11/15 ,  G11C11/401 ,  G11C11/407 ,  G11C11/02

Abstract: The data memory has the databanks (BK) stacked one behind the other, with their row edges parallel to one another, the ends of their column lines (BL) coupled to respective column control devices (LV,SS) lying in a common plane extending in the row direction, orthogonal to the column direction. The column control devices of all databanks are closely packed together as a block along the row edge of the databanks.

公开(公告)号：DE102005033480B4

公开(公告)日：2010-08-26

申请号：DE102005033480

申请日：2005-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN DANIEL ,  MUELLER GERHARD

IPC: H01L43/08 ,  H01L27/22

公开(公告)号：DE69834540T2

公开(公告)日：2007-05-03

申请号：DE69834540

申请日：1998-12-18

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G11C7/00 ,  G11C11/401 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14 ,  G11C11/408 ,  G11C11/409 ,  G11C16/06

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F , includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

公开(公告)号：DE102005031876A1

公开(公告)日：2007-01-11

申请号：DE102005031876

申请日：2005-07-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LIAW CORVIN ,  KUND MICHAEL ,  MUELLER GERHARD

IPC: G11B13/08

Abstract: A store with a storage device (2) and a write device (1) having at least one probe (10). The storage device (2) is a resistive storage device (2) with an active layer (11), where the active layer and the probe (10) are designed so that with application of electric signals via the probe (10) to the active layer (11) at least one zone (14) of the active layer is switched to and fro between a high- and a low-resistance state, in which each state is each resistance state is assigned a logic state.

公开(公告)号：DE10314615B4

公开(公告)日：2006-12-21

申请号：DE10314615

申请日：2003-04-01

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/22 ,  H03F3/04 ,  H03K19/0175 ,  H03K19/094

Abstract: A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

公开(公告)号：DE60010338T2

公开(公告)日：2005-06-16

申请号：DE60010338

申请日：2000-12-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  H03K17/22 ,  H03K19/0175

Abstract: A prefetch input write driver for a random access memory (RAM) and a RAM including the prefetch input write driver. The prefetch input write driver is especially for a synchronous dynamic RAM (SDRAM). The prefetch input write driver includes a data input stage receiving data, an enable stage receiving a corresponding data enable, and a write driver providing received data to a memory array in response to a write signal and the corresponding enable stage state. The data stage and the enable stage may each include two or more series connected three state drivers and a latch at the output of each three state driver. As data passes through the data stage a corresponding enable state is passed through the enable stage. Data is passed to the RAM array if the enable state indicates that data in the data stage is to be written into the array.

公开(公告)号：DE50106053D1

公开(公告)日：2005-06-02

申请号：DE50106053

申请日：2001-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD ,  SCHLOESSER TILL

IPC: H01L27/105 ,  G11C5/00 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/112

Abstract: An integrated memory with a configuration of non-volatile memory cells based on ferromagnetic storage contains both powerful memory cells with a magnetoresistive effect with a transistor control and cost-effective memory cells with a magnetoresistive effect with memory elements connected between the word lines and bit lines. The memory elements connected directly between the bit line and the word line are preferably inserted in memory cell arrays that can be stacked one above the other above the memory cells with the transistor, and thereby achieve a high integration density. The fact that the memory, which contains both types and thereby satisfies all the system requirements, is fabricated in one module and in one process sequence considerably lowers the fabrication costs.

公开(公告)号：DE60107219D1

公开(公告)日：2004-12-23

申请号：DE60107219

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： MUELLER GERHARD ,  HANSON DAVID R ,  BAILEY W

IPC: G11C5/06 ,  H03K19/0185 ,  H03K19/094 ,  G11C7/00 ,  H03K3/00

Abstract: A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.

公开(公告)号：DE69911102T2

公开(公告)日：2004-07-01

申请号：DE69911102

申请日：1999-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MUELLER GERHARD

IPC: G11C11/401 ,  G11C5/06 ,  G11C7/10 ,  G11C8/14 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C11/408 ,  G11C11/409

Abstract: A memory circuit having a stitched architecture wherein word lines of the memory circuit comprise a low resistance conductor stitched to a gate conductor portion having a higher resistance than the low resistance conductor. The memory circuit includes an array of memory cells having thereon bit lines disposed generally along a first direction and the word lines disposed generally along a second direction substantially orthogonal to the first direction. The memory circuit also includes an array sense amplifier region disposed adjacent the array of memory cells generally along the first direction. The array sense amplifier region has therein a plurality of array sense amplifiers coupled to the bit lines. The memory circuit further includes a stitch region containing contacts for stitching the low resistance conductor with the gate conductor. The stitch region is disposed adjacent the array of memory cells generally along the second direction. There is further included a set of local data lines disposed generally along the second direction and coupled to the plurality of array sense amplifiers. There is also included a set of master data switches coupled to the set of local data lines. The master data switch is disposed in a contact-free portion of the stitch region that is adjacent to the array sense amplifier region generally along the second direction. The memory circuit further includes a set of master data lines disposed generally along the first direction and a set of master line-to-switch connectors disposed generally along the second direction for coupling the set of master data lines to the set of master data switches, wherein the set of bit lines, the set of master data lines, the low resistance conductors of the word lines, the set of local data lines, and the set of master line-to-switch connectors are formed from at least four different conductor layers of the memory circuit.

公开(公告)号：DE60006720D1

公开(公告)日：2003-12-24

申请号：DE60006720

申请日：2000-12-04

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HANSON R ,  KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/10 ,  G11C7/00

Abstract: A random access memory (RAM) included in an integrated circuit and particularly a synchronous dynamic RAM (SDRAM) having a maskable data input. The SDRAM includes an xy data input register receiving a burst x bits long and y bits wide corresponding to the number of data lines (DQs). An xy mask register receives a corresponding mask bit for each received data bit, each mask bit indicating whether the corresponding data bit is stored in the SDRAM array. An enable buffer receives data outputs from the xy data input register and passes the individual data outputs to the array depending on corresponding mask states stored in the xy mask register. The mask register is preferably set to a masked state. Un masking occurs when an enable signal is asserted on a bit by bit basis. This allows the remaining bits within the burst length to be in a masked state when a write burst interrupt command is asserted. During an input prefetch, an interrupt may occur causing any received portion of the burst or prefetch to be stored in the array without disturbing memory locations corresponding to the balance or remaining bits of the prefetch.