公开(公告)号：DE50110560D1

公开(公告)日：2006-09-07

申请号：DE50110560

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

IPC: G11C11/00 ,  H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08

Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

公开(公告)号：DE10112281B4

公开(公告)日：2006-06-29

申请号：DE10112281

申请日：2001-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

IPC: G11C7/06 ,  G11C11/15 ,  G11C7/02 ,  G11C7/12 ,  G11C11/02 ,  G11C11/4091 ,  G11C11/419 ,  G11C16/26 ,  G11C17/18

Abstract: A memory sense amplifier for a semiconductor memory device is provided with a compensation current source device that generates a compensation current and feeds it to an interconnected bit line. The compensation current is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device on the selected and interlinked bit line device that is substantially constant over time.

公开(公告)号：AU2003294886A1

公开(公告)日：2004-07-14

申请号：AU2003294886

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR WILLIAM ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：DE10055936C2

公开(公告)日：2003-08-28

申请号：DE10055936

申请日：2000-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  HOENIGSCHMID HEINZ

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/14 ,  G11C11/15

Abstract: The form of leads of a cell array of a multiplicity of magnetic memory cells is optimized by deviating from a square cross section of the leads in such a way that the magnetic field component of the write currents lying in the cell array plane decreases sufficiently rapidly with increasing distance from the crossover point. The cell array is constructed from a matrix of the column leads and the row leads.

公开(公告)号：DE10118196C2

公开(公告)日：2003-02-27

申请号：DE10118196

申请日：2001-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  GOGL DIETMAR

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.

公开(公告)号：DE10037976C2

公开(公告)日：2003-01-30

申请号：DE10037976

申请日：2000-08-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: The voltage drop across a word line (VWL) is (V1-V2). A voltage controller applies a voltage (VBL) of (V1 + V2/2) to the bit lines (BLO-BL4). The voltage gradient across the word line (WL) relative to the bit line produces a cell voltage (VZ = VWL-VBL) which reverse along the memory cells. In consequence parasitic currents flow not through the word line but between cells (Z0-Z4) at corresponding positions relative to the center of the word line

公开(公告)号：DE10053965A1

公开(公告)日：2002-06-20

申请号：DE10053965

申请日：2000-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  LAMMERS STEFAN ,  FREITAG MARTIN ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: The arrangement has memory cells in a field in at least one plane at intersection points between word or programming lines and bit lines. Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the adjacent cell word, programming, bit or special line to produce a compensation magnetic field countering the stray field. The MRAM arrangement has memory cells (11-13) in a memory cell field in at least one plane at intersection points between word lines (WL1) or programming lines and bit lines (BL1-BL3). Providing programming currents to word and bit lines corresponding to a selected cell causes stray magnetic fields in adjacent cells. The method involves feeding a compensation current to the word line or programming line or bit line or a special line of the adjacent cell(s) to produce a compensation magnetic field countering the stray field.

公开(公告)号：DE102006001117B9

公开(公告)日：2009-04-16

申请号：DE102006001117

申请日：2006-01-09

Applicant: IBM ,  QIMONDA AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06 ,  G11C7/12 ,  H03F3/195

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

公开(公告)号：DE60320301T2

公开(公告)日：2009-06-25

申请号：DE60320301

申请日：2003-12-10

Applicant: IBM ,  QIMONDA AG

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE102006001117B4

公开(公告)日：2008-11-27

申请号：DE102006001117

申请日：2006-01-09

Applicant: IBM ,  QIMONDA AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06 ,  G11C7/12 ,  H03F3/195

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.