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    METHODS AND SYSTEMS TO MANAGE MACHINE STATE IN VIRTUAL MACHINE OPERATIONS
    42.
    发明申请
    METHODS AND SYSTEMS TO MANAGE MACHINE STATE IN VIRTUAL MACHINE OPERATIONS 审中-公开
    虚拟机操作中管理机器的方法和系统

    公开(公告)号：WO2004061659A3

    公开(公告)日：2005-07-28

    申请号：PCT/US0338728

    申请日：2003-12-04

    Applicant: INTEL CORP

    Inventor： BENNETT STEVEN ,  NEIGER GILBERT ,  COTA-ROBLES ERIK ,  JEYASINGH STALINSELVARAJ ,  KAGI ALAIN ,  KOZUCH MICHAEL ,  UHLIG RICHARD

    IPC: G06F9/455 ,  G06F9/46

    CPC classification number: G06F9/45558 ,  G06F2009/4557

    Abstract: Methods and systems are provided to control transitions between a virtual machine (VM) and Virtual Machine Monitor (VMM). A processor uses state action indicators to load and/or store associated elements of machine state before completing the transition. The state action indicators may be stored in a Virtual Machine Control Structure (VMCS), predetermined, and/or calculated dynamically. In some embodiments, the values loaded can be directly acquired from the VMCS, predetermined and/or calculated dynamically. In some embodiments, the values stored may be acquired directly from machine state, predetermined and/or calculated dynamically.

    Abstract translation: 提供了方法和系统来控制虚拟机（VM）和虚拟机监视器（VMM）之间的转换。 在完成转换之前，处理器使用状态动作指示器来加载和/或存储机器状态的相关元件。 状态动作指示符可以存储在虚拟机控制结构（VMCS）中，预定的和/或动态地计算。 在一些实施例中，可以从VMCS直接获取加载的值，预先确定和/或动态地计算。 在一些实施例中，存储的值可以直接从机器状态获取，预定和/或动态地计算。

    AVOIDING PREMATURE ENABLING OF NONMASKABLE INTERRUPTS WHEN RETURNING FROM EXCEPTIONS
    46.
    发明公开
    AVOIDING PREMATURE ENABLING OF NONMASKABLE INTERRUPTS WHEN RETURNING FROM EXCEPTIONS 审中-公开

    公开(公告)号：EP3198402A4

    公开(公告)日：2018-06-20

    申请号：EP15843881

    申请日：2015-08-31

    Applicant: INTEL CORP

    Inventor： ANVIN H PETER ,  NEIGER GILBERT

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F11/07 ,  G06F13/24

    CPC classification number: G06F13/24 ,  G06F9/327 ,  G06F9/4812 ,  G11C7/1072

    Abstract: A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.

    METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY
    48.
    发明申请
    METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY 审中-公开
    支持共享虚拟内存的异构计算系统中TLB SHOOT-DOWN的方法和设备

    公开(公告)号：WO2013016345A2

    公开(公告)日：2013-01-31

    申请号：PCT/US2012047991

    申请日：2012-07-24

    Applicant: INTEL CORP ,  SANKARAN RAJESH M ,  KOKER ALTUG ,  LANTZ PHILIP ,  MALLICK ASIT K ,  CROSSLAND JAMES B ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW V

    Inventor： SANKARAN RAJESH M ,  KOKER ALTUG ,  LANTZ PHILIP ,  MALLICK ASIT K ,  CROSSLAND JAMES B ,  NAVALE ADITVA ,  NEIGER GILBERT ,  ANDERSON ANDREW V

    IPC: G06F12/10 ,  G06F15/80

    CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

    Abstract: Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

    Abstract translation: 公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。 用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目 。 PASID状态条目可以包括活动参考状态和惰性无效状态。 响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。 存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。

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