公开(公告)号：WO2011078855A1

公开(公告)日：2011-06-30

申请号：PCT/US2009069212

申请日：2009-12-22

Applicant: INTEL CORP ,  MCKEEN FRANCIS X ,  ROZAS CARLOS V ,  SAVAGANKAR UDAY R ,  JOHNSON SIMON P ,  SCARLATA VINCENT R ,  GOLDSMITH MICHAEL A ,  BRICKELL ERNIE ,  LI JIANGTAO ,  HERBERT HOWARD C ,  DEWAN PRASHANT ,  TOLOPKA STEPHEN J ,  NEIGER GILBERT ,  DURHAM DAVID ,  GRAUNKE GARY ,  LINT BERNARD ,  VAN DYKE DON A ,  CIHULA JOSEPH ,  JEYASINGH STALINSELVARAJ ,  VAN DOREN STEPHEN R ,  RODGERS DION ,  GARNEY JOHN

Inventor： MCKEEN FRANCIS X ,  ROZAS CARLOS V ,  SAVAGANKAR UDAY R ,  JOHNSON SIMON P ,  SCARLATA VINCENT R ,  GOLDSMITH MICHAEL A ,  BRICKELL ERNIE ,  LI JIANGTAO ,  HERBERT HOWARD C ,  DEWAN PRASHANT ,  TOLOPKA STEPHEN J ,  NEIGER GILBERT ,  DURHAM DAVID ,  GRAUNKE GARY ,  LINT BERNARD ,  VAN DYKE DON A ,  CIHULA JOSEPH ,  JEYASINGH STALINSELVARAJ ,  VAN DOREN STEPHEN R ,  RODGERS DION ,  GARNEY JOHN

IPC: G06F9/44 ,  G06F12/02 ,  G06F13/14 ,  G06F21/72 ,  G06F21/74

CPC classification number: G06F12/1491 ,  G06F12/0802 ,  G06F12/10 ,  G06F21/72 ,  G06F21/74 ,  G06F2221/2105

Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

Abstract translation: 一种在计算机系统内实现安全应用和数据完整性的技术。 在一个实施例中，建立一个或多个安全空间，其中可以存储和执行应用和数据。

公开(公告)号：GB2515611A

公开(公告)日：2014-12-31

申请号：GB201405732

申请日：2014-03-31

Applicant: INTEL CORP

Inventor： ROZAS CARLOS V ,  ALEXANDROVICH ILYA ,  ANATI ITTAI ,  BERENZON ALEX ,  GOLDSMITH MICHAEL A ,  HUNTLEY BARRY E ,  IVANOV ANTON ,  JOHNSON SIMON P ,  LESLIE-HURD REBEKAH M ,  MCKEEN FRANCIS ,  NEIGER GILBERT ,  RAPPOPORT RINAT ,  RODGERS SCOTT ,  SAVAGAONKAR UDAY R ,  SCARLATA VINCENT R ,  SHANBHOGUE VEDVYAS ,  SMITH WESLEY H ,  WOOD WILLIAM COLIN

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/10 ,  G06F21/62

Abstract: A processor has multiple hardware threads and an enclave page cache. The processor has a first instruction to prevent new address translations being created. This instruction takes the address of a page in a secure enclave as a as a parameter. It prevents new entries being made in a translation look-aside buffer for that page. The processor has a second instruction to record the threads accessing an enclave. This instruction specifies the enclave identifier as a parameter and records the number of hardware threads accessing the enclave. The number is decremented whenever a thread exits the enclave. The processor has a third instruction to evict a page from an enclave page cache. The instruction takes the page address to evict as a parameter. It writes the page back to memory if the number of threads accessing the enclave is zero.

公开(公告)号：WO2010057065A3

公开(公告)日：2010-08-19

申请号：PCT/US2009064493

申请日：2009-11-14

Applicant: INTEL CORP ,  MCKEEN FRANK ,  SAVAGAONKAR UDAY ,  ROZAS CARLOS V ,  GOLDSMITH MICHAEL A ,  HERBERT HOWARD C ,  ALTMAN ASHER ,  GRAUNKE GARY ,  DURHAM DAVID ,  JOHNSON SIMON P ,  KOUNAVIS MICHAEL E ,  SCARLATA VINCENT R ,  CIHULA JOSEPH ,  JEYASINGH STALINSELVARAJ ,  LINT BERNARD ,  NEIGER GIL ,  RODGERS DION ,  BRICKELL ERNIE ,  LI JIANGUO

Inventor： MCKEEN FRANK ,  SAVAGAONKAR UDAY ,  ROZAS CARLOS V ,  GOLDSMITH MICHAEL A ,  HERBERT HOWARD C ,  ALTMAN ASHER ,  GRAUNKE GARY ,  DURHAM DAVID ,  JOHNSON SIMON P ,  KOUNAVIS MICHAEL E ,  SCARLATA VINCENT R ,  CIHULA JOSEPH ,  JEYASINGH STALINSELVARAJ ,  LINT BERNARD ,  NEIGER GIL ,  RODGERS DION ,  BRICKELL ERNIE ,  LI JIANGUO

IPC: G06F3/06 ,  G06F9/06 ,  G06F9/44 ,  G06F21/56

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F21/56

Abstract: A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an application and data may be stored and executed.

Abstract translation: 一种在计算机系统内实现安全应用程序和数据完整性的技术。 在一个实施例中，建立一个或多个安全区域，其中可以存储和执行应用程序和数据。

公开(公告)号：WO2006012291A3

公开(公告)日：2006-08-03

申请号：PCT/US2005022467

申请日：2005-06-22

Applicant: INTEL CORP ,  GOLDSMITH MICHAEL A

Inventor： GOLDSMITH MICHAEL A

IPC: G06F13/38 ,  G06F9/455 ,  G06F13/10

CPC classification number: G06F13/382

Abstract: A physical device has core function circuitry that is to perform a core I/O function of a computer system. Multiple client interface circuits are provided, each of which presents itself as a complete device to a software client in the system, to access the core function circuitry. Multiplexing circuitry couples the client interfaces to the core I/O functionality. Other embodiments are also described and claimed.

Abstract translation: 物理设备具有执行计算机系统的核心I / O功能的核心功能电路。 提供了多个客户端接口电路，每个客户端接口电路将其自身呈现为系统中的软件客户端的完整设备，以访问核心功能电路。 多路复用电路将客户端接口耦合到核心I / O功能。 还描述和要求保护其他实施例。

公开(公告)号：EP2870562A4

公开(公告)日：2016-03-09

申请号：EP13813182

申请日：2013-07-03

Applicant: INTEL CORP

Inventor： JANUS SCOTT ,  LAYTON KENNETH T ,  GOLDSMITH MICHAEL A

IPC: G06F21/84 ,  G06F21/32 ,  G06F21/62

CPC classification number: G06F21/31 ,  G06F21/32 ,  G06F21/6245 ,  G06F21/84 ,  H04L63/0861 ,  H04L2463/082

公开(公告)号：BRPI0924512A2

公开(公告)日：2016-03-01

申请号：BRPI0924512

申请日：2009-12-22

Applicant: INTEL CORP

Inventor： LINT BERNARD ,  ROZAS CARLOS V ,  DURHAM DAVID ,  RODGERS DION ,  DYKE DON A VAN ,  BRICKEL ERNIE ,  MCKEEN FRANCIS X ,  GRAUNKE GARY ,  NEIGER GILBERT ,  HERBERT HOWARD C ,  LI JIANG TAO ,  GARNEY JOHN ,  CIHULA JOSEPH ,  GOLDSMITH MICHAEL A ,  DEWAN PRASHANT ,  JOHNSON SIMON P ,  JEYASINGH STALINSELVARAJ ,  TOLOPKA STEPHEN J ,  DOREN STEPHEN R VAN ,  DOREN STEPHEN R VAN ,  SAVAGANKAR UDAY R ,  SCARLATA VINCENT R

IPC: G06F9/44 ,  G06F12/02 ,  G06F13/14 ,  G06F21/72 ,  G06F21/74

公开(公告)号：GB2528796A

公开(公告)日：2016-02-03

申请号：GB201515835

申请日：2015-04-01

Applicant: INTEL CORP

Inventor： ROZAS CARLOS V ,  ALEXANDROVICH ILYA ,  ANATI ITTAI ,  BERENZON ALEX ,  GOLDSMITH MICHAEL A ,  HUNTLEY BARRY E ,  JOHNSON SIMON P ,  LESLIE-HURD REBEKAH M ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RAPPOPORT RINAT ,  RODGERS SCOTT DION

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/1027 ,  G06F21/62

Abstract: A processor has multiple hardware threads and an enclave page cache. The processor has a first instruction to prevent new address translations being created. This instruction takes the address of a page in a secure enclave as a as a parameter. It prevents new entries being made in a translation look-aside buffer for that page. The processor has a second instruction to record the threads accessing an enclave. This instruction specifies the enclave identifier as a parameter and records the number of hardware threads accessing the enclave. The number is decremented whenever a thread exits the enclave. The processor has a third instruction to evict a page from an enclave page cache. The instruction takes the page address to evict as a parameter. It writes the page back to memory if the number of threads accessing the enclave is zero.

公开(公告)号：GB2515611B

公开(公告)日：2015-06-03

申请号：GB201405732

申请日：2014-03-31

Applicant: INTEL CORP

Inventor： ROZAS CARLOS V ,  ALEXANDROVICH ILYA ,  ANATI ITTAI ,  BERENZON ALEX ,  GOLDSMITH MICHAEL A ,  HUNTLEY BARRY E ,  IVANOV ANTON ,  JOHNSON SIMON P ,  LESLIE-HURD REBEKAH M ,  MCKEEN FRANCIS ,  NEIGER GILBERT ,  RAPPOPORT RINAT ,  RODGERS SCOTT DION ,  SAVAGAONKAR UDAY R ,  SCARLATA VINCENT R ,  SHANBHOGUE VEDVYAS ,  SMITH WESLEY H ,  WOOD WILLIAM COLIN

IPC: G06F12/14 ,  G06F9/30 ,  G06F12/10 ,  G06F21/62

公开(公告)号：GB2522137B

公开(公告)日：2015-12-02

申请号：GB201505638

申请日：2015-04-01

Applicant: INTEL CORP

Inventor： ROZAS CARLOS V ,  ALEXANDROVICH ILYA ,  ANATI ITTAI ,  BERENZON ALEX ,  GOLDSMITH MICHAEL A ,  HUNTLEY BARRY E ,  JOHNSON SIMON P ,  LESLIE-HURD REBEKAH M ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RAPPOPORT RINAT ,  RODGERS SCOTT DION ,  SAVAGAONKAR UDAY R ,  SCARLATA VINCENT R ,  SHANBHOGUE VEDVYAS ,  SMITH WESLEY H ,  WOOD WILLIAM COLIN ,  IVANOV ANTON

IPC: G06F12/08 ,  G06F9/30 ,  G06F12/10 ,  G06F21/62

公开(公告)号：GB2522137A

公开(公告)日：2015-07-15

申请号：GB201505638

申请日：2015-04-01

Applicant: INTEL CORP

Inventor： ROZAS CARLOS V ,  ALEXANDROVICH ILYA ,  ANATI ITTAI ,  BERENZON ALEX ,  GOLDSMITH MICHAEL A ,  HUNTLEY BARRY E ,  JOHNSON SIMON P ,  LESLIE-HURD REBEKAH M ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RAPPOPORT RINAT ,  RODGERS SCOTT DION ,  SAVAGAONKAR UDAY R ,  SCARLATA VINCENT R ,  SHANBHOGUE VEDVYAS ,  SMITH WESLEY H ,  WOOD WILLIAM COLIN ,  IVANOV ANTON

IPC: G06F12/08 ,  G06F9/30 ,  G06F21/62

Abstract: A processor has an enclave page cache to cache data from a secure enclave. An instruction (ETRACK) causes it to record the number of hardware threads accessing the data in the cache corresponding to the secure enclave. This may be the threads, which are executing code in the secure enclave. When any of the threads exits the secure enclave, the number is decremented. A second instruction (EWB) may cause the data in the cache to be evicted and written back to main memory when the number reaches zero. A third instruction (EBLOCK) may prevent the creation of new address translation entries for the pages in the cache. The data may be encrypted, when written to main memory, and decrypted, when read from main memory.