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41.发明申请SUB-WAVELENGTH EXTREME ULTRAVIOLET METAL TRANSMISSION GRATING AND MANUFACTURING METHOD THEREOF 有权亚波长极限超紫外线金属传输光栅及其制造方法公开(公告)号：US20140177039A1
公开(公告)日：2014-06-26
申请号：US14144222
申请日：2013-12-30
Inventor： Hailiang Li , Changqing Xie , Ming Liu , Dongmei Li , Lina Shi , Xiaoli Zhu
IPC: G02B5/18
CPC classification number: G02B5/1871 , G02B5/1809 , G02B5/1838 , G02B5/1857 , G02B2005/1804 , G03F7/0757 , G03F7/2059 , G03F7/40
Abstract: A method of manufacturing a sub-wavelength extreme ultraviolet metal transmission grating is disclosed. In one aspect, the method comprises forming a silicon nitride self-supporting film window on a back surface of a silicon-based substrate having both surfaces polished, then spin-coating a silicon nitride film on a front surface of the substrate with an electron beam resist HSQ. Then, performing electron beam direct writing exposure on the HSQ, developing and fixing to form a plurality of grating line patterns and a ring pattern surrounding the grating line patterns. Then depositing a chrome material on the front surface of the substrate through magnetron sputtering. Then, removing the chrome material inside the ring pattern. Then, growing a gold material on the front surface of the substrate through atomic layer deposition. Lastly, removing the gold material on the chrome material outside the ring pattern as well as on and between the grating line patterns, thereby only retaining the gold material on sidewalls of the grating line patterns.
Abstract translation: 公开了一种制造亚波长极紫外金属透射光栅的方法。 在一个方面，该方法包括在硅衬底的背表面上形成氮化硅自支撑膜窗，其两面被抛光，然后用电子束在衬底的前表面上旋涂氮化硅膜 抵制HSQ。 然后，在HSQ上执行电子束直接写入曝光，显影和固定以形成围绕光栅线图案的多个光栅线图案和环形图案。 然后通过磁控溅射在基板的前表面上沉积铬材料。 然后，移除环形图案内的铬材料。 然后，通过原子层沉积在基板的前表面上生长金材料。 最后，除去环形图案之外的铬材料上的金材料以及光栅线图案之间和之间的金材料，从而仅将金材料保留在光栅线图案的侧壁上。
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公开(公告)号：US12293781B2
公开(公告)日：2025-05-06
申请号：US18261716
申请日：2021-01-21
Inventor： Huai Lin , Guozhong Xing , Zuheng Wu , Long Liu , Di Wang , Cheng Lu , Peiwen Zhang , Changqing Xie , Ling Li , Ming Liu
IPC: G11C11/16
Abstract: The three-state spintronic device includes: a bottom electrode, a magnetic tunnel junction and a top electrode from bottom to top. The magnetic tunnel junction includes: a spin-orbit coupling layer, a ferromagnetic free layer, a barrier tunneling layer, a ferromagnetic reference layer, three local magnetic domain wall pinning centers and domain wall nucleation centers. An antisymmetric exchange interaction is modulated, and the magnetic domain wall pinning centers are embedded in an interface between a heavy metal and the ferromagnetic free layer. The magnetic domain wall nucleation centers are at two ends of the ferromagnetic free layer. A current pulse flows through the spin-orbit coupling layer to generate a spin current and the spin current is injected into the ferromagnetic free layer. Under a control of all-electrical controlled, an effective field of a spin-orbit torque drives domain wall to move and displace.
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43.发明申请公开(公告)号：US20250089577A1
公开(公告)日：2025-03-13
申请号：US18552786
申请日：2022-07-12
Inventor： Guozhong Xing , Hao Zhang , Xuefeng Zhao , Ziwei Wang , Changqing Xie , Ming Liu
IPC: H10N50/10 , H10B61/00 , H10N30/853 , H10N50/01 , H10N50/85
Abstract: The memory cell includes: a piezoelectric substrate layer, wherein two ends of the piezoelectric substrate layer are respectively provided with a first electrode and a second electrode, and a current-free drive of skyrmion is implemented by applying a voltage to the first electrode and the second electrode; a magnetic layer on a surface of the piezoelectric substrate layer, wherein the magnetic layer is used to form a heterojunction with the piezoelectric substrate layer, and is used to generate, stabilize, and serve as a basic carrier for a movement of the skyrmion; wherein the magnetic layer includes a convex body, the convex body is configured to divide the magnetic layer into a bit region and a memory region, and the bit region is provided with a magnetic tunnel junction used to perform generation and detection functions of the skyrmion.
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公开(公告)号：US12205630B2
公开(公告)日：2025-01-21
申请号：US18005101
申请日：2020-08-24
Inventor： Qing Luo , Bing Chen , Hangbing Lv , Ming Liu , Cheng Lu
IPC: G11C11/4096 , G11C11/408 , G11C11/4094 , H03K19/017
Abstract: Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.
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公开(公告)号：US12124945B2
公开(公告)日：2024-10-22
申请号：US17310203
申请日：2019-01-28
Inventor： Hangbing Lv , Xiaoxin Xu , Qing Luo , Ming Liu
CPC classification number: G06N3/065 , G11C11/223 , G11C11/2273 , G11C11/54 , H01L29/516 , H01L29/78391
Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.
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Patent Agency Ranking
公开(公告)号：US20240005077A1
公开(公告)日：2024-01-04
申请号：US18250461
申请日：2020-10-30
Inventor： Nianduan Lu , Ling Li , Wenfeng Jiang , Di GENG , Jiawei Wang , Ming Liu
CPC classification number: G06F30/39 , G16C60/00 , H01L29/786
Abstract: A method of designing a thin film transistor device, including: calculating characteristic parameters of searched materials; screening the materials according to a characteristic parameter threshold to obtain first active layer materials; simulating the first active layer material as an active layer material in a thin film transistor device model to obtain a device characteristic of the thin film transistor device; screening the first active layer materials according to a device characteristic threshold to obtain second active layer materials; taking the second active layer material as the active layer material of the thin film transistor device to perform an experiment; and selecting another second active layer material to perform the experiment once again when an experiment result does not meet a preset requirement, and a design of the thin film transistor device is completed until the experiment result meets the preset requirement.
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47.发明公开公开(公告)号：US20230397504A1
公开(公告)日：2023-12-07
申请号：US18249805
申请日：2021-05-17
Inventor： Guozhong Xing , Di Wang , Ming Liu
CPC classification number: H10N52/101 , H10N52/85 , H10N59/00 , G06N3/063
Abstract: Provided is an all-electrically-controlled spintronic neuron device, a neuron circuit and a neural network. The neuron device includes: a bottom antiferromagnetic pinning layer; a synthetic antiferromagnetic layer formed on the bottom antiferromagnetic pinning layer; a potential barrier layer formed on the ferromagnetic free layer, wherein a region of the ferromagnetic free layer directly opposite to the potential barrier layer forms a threshold region; a ferromagnetic reference layer formed on the potential barrier layer; wherein the potential barrier layer, the ferromagnetic reference layer and the ferromagnetic free layer form a magnetic tunnel junction; a first antiferromagnetic pinning layer and a second antiferromagnetic pinning layer formed on an exposed region of the ferromagnetic free layer except the region directly opposite the potential barrier layer, and located on two sides of the potential barrier layer; and a first electrode formed on the ferromagnetic reference layer.
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公开(公告)号：US20230276637A1
公开(公告)日：2023-08-31
申请号：US18003038
申请日：2020-06-24
Inventor： Guozhong Xing , Huai Lin , Ming Liu
Abstract: Provided are a spin orbit torque magnetic random access memory cell, a memory array and a memory, wherein the spin orbit torque magnetic random access memory cell includes: a magnetic tunnel and a selector; the selector is a two-dimensional material based selector; the magnetic tunnel junction is arranged above or below the selector; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer; the free layer is adjacent to the antiferromagnetic layer; when the selector is turned on, the memory cell is conducted, a current generates a spin current which is injected into the free layer, and a magnetization direction of the free layer is switched by the exchange bias effect between the free layer and the antiferromagnetic layer. A deterministic magnetization switching of SOT-MRAM memory cell under zero magnetic field at room temperature may be implemented without an external magnetic field by using the exchange bias effect and applying an optimized bias voltage of the magnetic tunnel junction, so as to achieve a purpose of data writing and implement SOT-MRAM memory cell with double terminal structure.
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公开(公告)号：US11294660B2
公开(公告)日：2022-04-05
申请号：US16337978
申请日：2017-04-21
Inventor： Yuanlu Xie , Kun Zhang , Haitao Sun , Jing Liu , Jinshun Bi , Ming Liu
IPC: G06F8/654 , G06F1/3296 , G06F13/42 , G06F8/71
Abstract: An apparatus and a method for configuring or updating a programmable logic device are provided. The apparatus includes a control module and a storage module connected to the control module. The control module includes: a JTAG interface for connecting the control module to a JTAG host, and a configuration interface compatible with a to-be-configured programmable logic device. The control module is configured to: after receiving a first control instruction including configuration information via the JTAG interface, store the configuration information into the storage module; and after receiving a configuration instruction, read the configuration information to configure the to-be-configured programmable logic device. A configuration clock used in a process that the control module configures the to-be-configured programmable logic device is generated from the to-be-configured programmable logic device, the control module or an external clock source.
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公开(公告)号：US11215652B2
公开(公告)日：2022-01-04
申请号：US16065582
申请日：2015-12-25
Inventor： Guangwei Xu , Zhiheng Han , Wei Wang , Congyan Lu , Lingfei Wang , Ling Li , Ming Liu
Abstract: A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes. The invention has the advantages of reasonable theory, accurate result, simple and easy operation, and is favorable for optimizing the device performance and establishing a complete electrical model of the device.
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