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公开(公告)号：AU2017335889A1
公开(公告)日：2019-03-07
申请号：AU2017335889
申请日：2017-09-28
Applicant: QUALCOMM INC
Inventor： ANG PETER PUI LOK , MUKKAVILLI KRISHNA KIRAN , CHALLA RAGHU , YANG YANG , GOROKHOV ALEXEI YURIEVITCH , JI TINGFANG , SORIAGA JOSEPH BINAMIRA , LEE HEECHOON
Abstract: Techniques are described for wireless communication. A method for wireless communication at a user equipment (UE) includes identifying a transmission timing of a control reference signal transmitted over a radio frequency spectrum band during an OFF duration of the UE with respect to the radio frequency spectrum band, in which the identified transmission timing is relative to a transition from the OFF duration to an ON duration of the UE with respect to the radio frequency spectrum band; receiving the control reference signal at the identified transmission timing; and performing a warm-up procedure, before the ON duration, based at least in part on the identified transmission timing of the control reference signal. A method for wireless communication at a wireless network includes indicating, to the UE, the transmission timing of the control reference signal; and transmitting the control reference signal at the indicated transmission timing. The OFF duration and the ON duration are coordinated with a wireless network.
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公开(公告)号：CA2723046C
公开(公告)日：2013-02-19
申请号：CA2723046
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC: H03G1/00 , H04B1/16 , H03G3/00 , H03G3/20 , H03G3/30 , H04B1/30 , H04J13/00 , H04L27/22 , H04L27/38
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：CA2438333C
公开(公告)日：2011-11-01
申请号：CA2438333
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT CHRISTOPHER
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：UA84130C2
公开(公告)日：2008-09-25
申请号：UA20041008806
申请日：2003-03-26
Applicant: QUALCOMM INC
Inventor： BLACK PETER J , SINDKHUSHAYANA NAGABKHUSHANA , CHALLA RAGHU , SELTMANN KEVIN
Abstract: Системыи способырегулированияусилениявключаютусилениесигналаусилителем, которыйимееткоэффициентусиления, которыйпредставленоднойизмножестваамплитудныххарактеристик, которыезависятотвеличиныпараметра, причемсигналусиливаетсянапервойвеличинепараметра, ирегулированиеусиленияусиленногосигналав соответствиис заданнойамплитудойхарактеристики, которыйотноситсяк амплитуднойхарактеристикеусилителядлядругойвеличиныпараметра, путемкоррекциисигналарегулированияусиления, которыйсоответствуетточкенакривойзаданнойамплитуднойхарактеристики, какфункциипервойвеличиныпараметра, иподачускорректированногосигналарегулированияусилениянаусилитель. Обращаетсявниманиенато, чтоданныйрефератсостав�
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公开(公告)号：DE60321898D1
公开(公告)日：2008-08-14
申请号：DE60321898
申请日：2003-03-26
Applicant: QUALCOMM INC
Inventor： BLACK PETER J , SINDHUSHAYANA NAGABHUSHANA , CHALLA RAGHU , SELTMANN KEVIN
Abstract: Systems and techniques for gain control include amplifying a signal with an amplifier having a gain represented by one of a plurality of gain curves depending on a value of a parameter, the signal being amplified at a first one of the parameter values, and controlling the gain of the amplified signal from a predetermined gain curve relating to the gain curve of the amplifier for a second one of the parameter values by adjusting a gain control signal corresponding to a point on the predetermined gain curve as a function of the first one of the parameter values, and applying the adjusted gain control signal to the amplifier. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
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Patent Agency Ranking
公开(公告)号：AU2007224396A1
公开(公告)日：2007-11-01
申请号：AU2007224396
申请日：2007-10-15
Applicant: QUALCOMM INC
Inventor： KANG INJUP , HOLENSTEIN CHRISTIAN , CHALLA RAGHU , WALKER BRETT C , SIH GILBERT C , LI TAO , SEVERSON MATTHEW L , RAGHUPATHY ARUN , PETERZELL PAUL E
Abstract: An apparatus and method in a wireless communication system, the apparatus comprising: first means for amplifying a received signal; means for cancelling a DC offset in the amplified signal; second means for digitally amplifying the DC offset cancelled signal; and means for measuring the digitally amplified signal and to control the gains of the first and second amplifying means.
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公开(公告)号：BR0307367A
公开(公告)日：2005-04-26
申请号：BR0307367
申请日：2003-01-31
Applicant: QUALCOMM INC
Inventor： CHALLA RAGHU , ROH MARK CHARLES , PATEL SHIMMAN
Abstract: Techniques to acquire the frequency of a signal instance based on a window of data samples covering a time period shorter than the time needed to achieve frequency lock. The window of data samples is initially captured and stored to a sample buffer. A segment of data samples is then retrieved from the sample buffer for processing. The retrieved data samples are rotated by a current frequency error estimate to provide frequency-translated data samples, which are further processed to provide one or more pilot symbols. An updated frequency error estimate for the frequency-translated data samples is then derived based on the pilot symbols using a frequency control loop. The window of data samples is processed for a number of iterations until frequency acquisition is achieved for the signal instance or termination is reached. For each iteration, one segment is processed at a time and typically in sequential order.
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公开(公告)号：MXPA03005105A
公开(公告)日：2004-05-24
申请号：MXPA03005105
申请日：2000-12-07
Applicant: QUALCOMM INC
Inventor： CHALLA RAGHU
Abstract: Se describe un metodo y aparato para rastrear el largo de un periodo de reposo en una estacion movil que utiliza un reloj de reposo para calibrar con precision porciones del periodo de reposo. El periodo de reposo se subdivide en una secuencia de sub-periodos cada uno de duracion conocida en el que las duraciones de los sub-periodos no son necesariamente multiplos enteros de los ciclos del reloj de reposo. El tiempo transcurrido se rastrea en cada sub-periodo individual del periodo de reposo utilizando un contador de reposo da enteros el cual rastrea todos los ciclos del reloj de reposo. Despues se rastrea cualquier porcion fraccional restante de los ciclos del reloj de modo de reposo no contabilizada por el contador de reposo de enteros utilizando un contador de reposo fraccional. El contador de reposo fraccional acumula las porciones fraccionales restantes de ciclos de modo de reposo de un sub-periodo al siguiente. Se describen tambien un metodo y aparato para calcular la variacion de frecuencia con una senal de reloj de reposo utilizada durante un modo de operacion de llamada ranurada de una estacion movil inalambrica. Se determina una frecuencia inicial de la senal de reloj de reposo despues del encendido de la estacion movil. Despues se determina un factor de compensacion de variacion de frecuencia fija representativo de una diferencia entre la frecuencia inicial de la senal de reloj de reposo y una frecuencia nominal pre-determinada. Se calcula un factor de compensacion de error de frecuencia dinamica representativo de una diferencia entre la frecuencia inicial y una frecuencia actual de la serial de reloj lento. Despues, mediante el modo de operacion ranurado, se determinan iterativamente valores nuevos para el factor de compensacion de frecuencia dinamica utilizando un filtro de lazo.
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公开(公告)号：CA2476318A1
公开(公告)日：2003-10-09
申请号：CA2476318
申请日：2003-03-26
Applicant: QUALCOMM INC
Inventor： SELTMANN KEVIN , CHALLA RAGHU , BLACK PETER J , SINDHUSHAYANA NAGABHUSHANA
Abstract: Systems and techniques for gain control include amplifying a signal with an amplifier having a gain represented by one of a plurality of gain curves depending on a value of a parameter, the signal being amplified at a first o ne of the parameter values, and controlling the gain of the amplified signal fr om a predetermined gain curve relating to the gain curve of the amplifier for a second one of the parameter values by adjusting a gain control signal corresponding to a point on the predetermined gain curve as a function of th e first one of the parameter values, and applying the adjusted gain control signal to the amplifier. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
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公开(公告)号：CA2723046A1
公开(公告)日：2002-08-29
申请号：CA2723046
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC: H03G1/00 , H04B1/16 , H03G3/00 , H03G3/20 , H03G3/30 , H04B1/30 , H04J13/00 , H04L27/22 , H04L27/38
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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