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    MESA TYPE TRIAC
    41.
    发明专利
    MESA TYPE TRIAC 失效

    公开(公告)号：JPH02114669A

    公开(公告)日：1990-04-26

    申请号：JP26888188

    申请日：1988-10-25

    Applicant: SHARP KK

    Inventor： YOSHIKAWA TOSHIBUMI ,  KOYAMA JUNICHIRO

    IPC: H01L29/74 ,  H01L29/06 ,  H01L29/747

    Abstract: PURPOSE:To prevent the occurrence the cracks in a water by a method wherein a mesa type triac is provided with a second layer of a second conductive type which is not only in contact with a mesa groove but also formed on a part of the surface of the second conductivity type first layer, where the second layer is smaller than the second conductivity type first layer in thickness and higher than impurity concentration respectively. CONSTITUTION:When a first conductivity type layer and a second conductivity type layer are formed on an N-type and a P-type semiconductor respectively, a mesa type triac is provided with the following; an N-type substrate 11; a mesa groove 15 formed on both the sides of the substrate 11 and coated with a glass passivation 16; a P -gate diffusion layer 12 formed on the surface of the N-type substrate 11 not in contact with the mesa groove 15; N -diffussion layers 14 formed on a part of the surface of the diffusion layer 12; and a P -compensation diffusion layer 13 which is formed on a part of the surface of the P -gate diffusion layer 12 and whose thickness is larger than that of the P gate diffusion layer 12 and impurity concentration is 2-10 times as high as that of the layer 12. Therefore, the thickness of a wafer remaining after a mesa groove is formed can be made large keeping the wafer excellent in breakdown strength without varying it in a current property or the like and the wafer can be protected from cracks.

    SEMICONDUCTOR DEVICE
    45.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS62115771A

    公开(公告)日：1987-05-27

    申请号：JP25550285

    申请日：1985-11-14

    Applicant: SHARP KK

    Inventor： KUBO MASARU ,  YOSHIKAWA TOSHIBUMI

    IPC: H01L29/73 ,  H01L21/331 ,  H01L29/72

    Abstract: PURPOSE:To reduce a time for storage of minority carriers so as to attain high speed by a construction wherein a diffused layer of a reverse conductivity type formed for reduction of collector serial resistance on the lower side of a base diffused layer of some conductivity type is made to have a partial region not overlapping with the base diffused layer, in a bipolar transistor formed on a substrate of this conductivity type. CONSTITUTION:An N-type diffused layer 2 for reducing collector serial resistance, which is formed on a P-type substrate 1, for instance, is laid on the lower side of a collector layer 4a and a diffused layer 3 which are of the same N-type, and a region 13 equivalent to about 1/2 of the lower side of the collector layer 4a is formed on the substrate 1 in contact therewith so that it does not overlap partially with a P-type base diffused layer 6 when viewed in plan. In the right-half region of the N-type collector layer 4a wherein the N-type diffused layer 3 exists, minority carriers inside the collector layer 4a are confined therein by an incorporated electric field, while in the left-half region wherein the N diffused layer 3 does not exist, the minority carriers inside the collector layer 4a are drawn into the substrate 1 and an isolated diffused layer 5, since the collector layer 4a is reversely biased with the substrate 1 and the isolated diffused layer 5. Therefore, the time required for extinction of the minority carriers is reduced sharply.

    POWER MOS-FET
    46.
    发明专利
    POWER MOS-FET 失效

    公开(公告)号：JPS6263472A

    公开(公告)日：1987-03-20

    申请号：JP20390085

    申请日：1985-09-13

    Applicant: SHARP KK

    Inventor： KUBO MASARU ,  OKADA KEIICHI ,  YOSHIOKA MINORU ,  ITO TAKUYA ,  YOSHIKAWA TOSHIBUMI

    IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

    Abstract: PURPOSE:To reduce ON resistance, by forming a groove in the back surface of a semiconductor substrate layer beneath a gate so that the groove penetrates through the substrate layer and cuts into an epitaxial layer, and forming a high concentration layer having the same conductivity type as the substrate layer in the substrate layer facing a drain electrode. CONSTITUTION:Anisotropic etching is performed in the back surface of a substrate layer 1 beneath each gate, and a groove 11 is formed. A high concentration N layer 12 is formed from the back surface side of the substrate layer 1, in which the groove 11 is formed. A drain electrode 10 is formed on the surface of the N layer 12. The groove 11 has the depth penetrating at least the substrate layer 1 and reaching an epitaxial layer 2. It is desirable that the depth of the groove is made as deep as possible in decreasing the ON resistance within a range the withstanding voltage can be maintained.

    SEMICONDUCTOR DEVICE
    50.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPS60241277A

    公开(公告)日：1985-11-30

    申请号：JP9802984

    申请日：1984-05-15

    Applicant: SHARP KK

    Inventor： YOSHIKAWA TOSHIBUMI ,  KUBO MASARU ,  KAGISAWA ATSUSHI ,  NISHIMOTO NOBUHIRO

    IPC: H01L27/14 ,  H01L27/144 ,  H01L31/10 ,  H01L31/11

    Abstract: PURPOSE:To obtain high reliability by a method wherein a wavelength discrimination element made of the series reverse-connection of two photodiodes is made integral with a signal processing circuit. CONSTITUTION:The wavelength discrimination element is constructed by reversely connecting two photodiodes PD1 and PD2 in series. The photodiode PD1 consists of a P type layer 15 and an N type layer 13, and the photodiode PD2 consists of a P type substrate 11 and the layer 13. When light is absorbed to a point B, the distribution of photocurrent to PD1 and PD2 becomes reversely proportional to the distance to the P type layers 14 and 15. The transistor of a bipolar IC part consitutes the signal processing circuit by the formation of an N type layer 17, an N type epitaxial layer 13, and N type regions 18 and 19.

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