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    41.
    发明专利
    未知

    公开(公告)号：ITVA20020020A1

    公开(公告)日：2003-09-04

    申请号：ITVA20020020

    申请日：2002-03-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASTALDO ENRICO ,  CONTE ANTONINO

    IPC: H02M3/07

    Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.

    42.
    发明专利
    未知

    公开(公告)号：ITMI20002763A1

    公开(公告)日：2002-06-20

    申请号：ITMI20002763

    申请日：2000-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONTE ANTONINO ,  LA ROCCA ROSANNA MARIA ,  MATRANGA GIOVANNI

    IPC: G11C16/28

    Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

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