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    41.
    发明专利
    未知

    公开(公告)号：ITMI992624D0

    公开(公告)日：1999-12-17

    申请号：ITMI992624

    申请日：1999-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G11C11/56

    Abstract: A read timing circuit regulates the step of reading from a multi-level non-volatile memory, which circuit is of a type adapted to generate and issue an equalization signal to a sense amplifier placed downstream of a dummy path including at least one dummy wordline, the latter being applied a supply voltage and associated with a dummy decoding circuit portion which receives an ATD signal. The circuit comprises a differential cell comparator having a first input connected downstream of the dummy path and a second input to receive a reference signal, thereby generating an electric signal on an output upon the dummy wordline attaining a potential which is a predetermined percent of the supply voltage.

    45.
    发明专利
    未知

    公开(公告)号：DE602006011005D1

    公开(公告)日：2010-01-21

    申请号：DE602006011005

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI

    IPC: G11C16/08 ,  G11C8/08

    Abstract: A non-volatile memory device is provided. The memory device includes a memory matrix (105; 605) comprising a plurality of memory cells (Mc), arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines (WL(i)); each word line is associated with one respective row of said plurality and is connected to the memory cells of the row; the word lines are grouped into at least one packet (WLP). The memory device includes a row selector (160; 660) coupled to the word lines and adapted to selectively biasing them. The row selector includes, for each packet of word lines, a plurality of first paths, wherein each first path is adapted to apply a first biasing voltage to a corresponding word line of the packet depending on an operation to be performed on the memory cells connected to the corresponding word line. Each first path includes at least a first (N(i)) and a second (P(i)) selection transistors series-connected between a first terminal and a second terminal of the first path. The second terminal is coupled to the corresponding word line. The memory device further includes enabling means (110) for commonly providing an enabling voltage to the first terminal of the first paths associated to a selected packet of word lines including a selected word line. The enabling voltage depends on the operation to be performed on the memory cells connected to the selected word line and is adapted to enable the execution of said operation. The memory device further includes selection means (150) for selecting one among said plurality of first paths. the selected first path corresponding to the selected word line. The selection means are adapted to activate the first selection transistor of the selected first path in order to obtain the first biasing voltage from the enabling voltage by a voltage drop introduced by the first selection transistor; said selection means are further adapted to activate the second selection transistor of the selected first path in order to transfer the first biasing voltage provided by the first selection transistor onto the selected word line.

    46.
    发明专利
    未知

    公开(公告)号：DE602006008480D1

    公开(公告)日：2009-09-24

    申请号：DE602006008480

    申请日：2006-09-13

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  RAVASIO ROBERTO ,  MARELLI ALESSIA

    IPC: G06F11/10 ,  G06F11/20

    Abstract: Basic redundancy information is non volatily stored in a reserved area (that is an area of the array that is not addressable by the user of the device) of the addressable area of the array and is copied on volatile storage supports at every power-on of the memory device. The unpredictable though statistically inevitable presence of fail array elements also in such a reserved area of the memory array that would corrupt the basic redundancy information as established during the test-on wafer (EWS) phase of the fabrication process and thus increasing the number of rejects, lowering the yield of the fabrication process, is effectively overcome by writing the basic redundancy data in the reserved area of the array with an ECC technique, using a certain error correction code that may be chosen among so-called majority codes 3, 5, 7, 15 and the like or Hamming code for 1, 2, 3 or more errors, in function of the fail probability of a memory cell as determined by the testing on wafer of the devices during fabrication (fail probability of the specific fabrication process used). A significant area saving is achieved compared to the use of fuse arrays and other known approaches.

    47.
    发明专利
    未知

    公开(公告)号：DE602005008396D1

    公开(公告)日：2008-09-04

    申请号：DE602005008396

    申请日：2005-05-20

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： RAGONE GIANCARLO ,  CRIPPA LUCA ,  SANGALLI MIRIAM ,  MICHELONI RINO

    IPC: G11C8/08 ,  G11C16/08 ,  H02M3/07 ,  H03K17/06

    Abstract: A high-voltage switch (24) has a high-voltage input terminal (29), receiving a high voltage (HV), and an output terminal (31). A pass transistor (36), having a control terminal, is connected between the high-voltage input terminal (29) and the output terminal (31). The output of a voltage-multiplying circuit (40) of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit (40) is of a symmetrical type, has first and second charge-storage means (41, 42), receiving a clock signal (CK) of a periodic type, and has a first circuit branch (44, 48) and a second circuit branch (45, 49), which are symmetrical to one another and operate in phase opposition with respect to the clock signal (CK).

    49.
    发明专利
    未知

    公开(公告)号：DE69937559D1

    公开(公告)日：2007-12-27

    申请号：DE69937559

    申请日：1999-09-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  SACCO ANDREA ,  MOGNONI SABINA

    IPC: G01R31/02 ,  G11C29/00 ,  G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G11C17/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

    Abstract: The non volatile memory device integrates, in one and the same chip (100), the array (2) of memory cells, a voltage regulator (REG) which supplies a regulated operating voltage (Vr) to a selected word line (LWL1), and a short circuit detecting circuit (10). The short circuit detecting circuit detects the output voltage (IM1) of the voltage regulator (REG), which is correlated to the current (Iw) for biasing the cells (3) of the word line selected (LWL1). Once settled to the steady state condition, the output current (IM1) assumes one first value (IM1') in the absence of short circuits, and one second value (IM1") in the presence of a short circuit between the word line selected (LWL1) and one or more adjacent word lines (LWL0, LWL2, ..., LWLn). The short circuit detecting circuit (10) compares the output current (IM1) of the voltage regulator (REG) with a reference value (Iref) and generates at output a short circuit digital signal (Vo) which indicates the presence or otherwise of a short circuit.

    50.
    发明专利
    未知

    公开(公告)号：DE60212332D1

    公开(公告)日：2006-07-27

    申请号：DE60212332

    申请日：2002-04-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  LOSAVIO ALDO

    IPC: G11C29/00

    Abstract: The self-repair method for a nonvolatile memory (1) intervenes at the end of an operation of modification, selected between programming and erasing, in the event of detection of just one non-functioning cell (14a, 14c), and carries out redundancy of the non-functioning cell. To this end, the memory array (15) is divided into a basic portion (20), formed by a plurality of memory cells (14a) storing basic data, and into a on-the-field redundancy portion (21), said on-the-field redundancy portion (21) being designed to store redundancy data including a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a purposely designed redundancy replacement circuit (12) and a purposely designed redundancy data verification circuit (7b).

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