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    41.
    发明专利
    未知

    公开(公告)号：DE69531823D1

    公开(公告)日：2003-10-30

    申请号：DE69531823

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

    IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

    42.
    发明专利
    未知

    公开(公告)号：IT1318979B1

    公开(公告)日：2003-09-19

    申请号：ITMI20002165

    申请日：2000-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C7/10 ,  G11C8/12 ,  G11C16/08

    Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

    43.
    发明专利
    未知

    公开(公告)号：ITMI20012795A1

    公开(公告)日：2003-06-24

    申请号：ITMI20012795

    申请日：2001-12-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: H03M5/00

    Abstract: A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example.

    44.
    发明专利
    未知

    公开(公告)号：IT1313847B1

    公开(公告)日：2002-09-24

    申请号：ITMI992465

    申请日：1999-11-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C8/10

    Abstract: A decoder with reduced complexity includes at least one OR circuit section and at least one AND circuit section. The at least one OR circuit section may include first and second circuit lines mutually connected and respectively receiving as inputs an address signal and an inverted address signal. The at least one AND circuit section may include first and second circuit lines which respectively receive as inputs the inverted address signal and the address signal. The at least one OR circuit section and the at least one AND circuit section may be connected to first and second booster circuits. Furthermore, the at least one OR circuit section may also include a virtual ground.

    46.
    发明专利
    未知

    公开(公告)号：ITMI20011311D0

    公开(公告)日：2001-06-21

    申请号：ITMI20011311

    申请日：2001-06-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C16/28

    Abstract: A dynamic or non-volatile memory with a differential reading system with improved load rebalancing comprising a rebalancing circuit that for values of the supply and memory selection voltage in excess of a predetermined reference voltage modifies one or the other of two currents, i.e., the measuring current or the reference current, with an equivalent effect on the load rebalancing.

    48.
    发明专利
    未知

    公开(公告)号：DE69518632T2

    公开(公告)日：2001-05-03

    申请号：DE69518632

    申请日：1995-06-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI

    IPC: G11C11/413 ,  G11C8/10 ,  G11C8/00

    Abstract: A bit line selection decoder, particularly for electronic memories, comprising at least two bit lines, each of which can be selected by a respective switch, and a plurality of control lines that drive the switches. Its particularity resides in the fact that it comprises a decoder, in which the outputs drive the switches, and at least one first and one second bus of control lines that are arranged in input to the decoder and are adapted to address any one of the at least two bit lines.

    50.
    发明专利
    未知

    公开(公告)号：DE69422794T2

    公开(公告)日：2000-06-08

    申请号：DE69422794

    申请日：1994-02-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PADOAN SILVIA ,  PASCUCCI LUIGI

    IPC: G11C17/00 ,  G11C16/06 ,  H01L27/10 ,  H03K19/177

    Abstract: The PLA (1), which implements a state machine of a nonvolatile memory, presents a dynamic NAND-NOT-NOR configuration, and the timing signals for correct reading of the PLA are generated by a clock generator (30) which generates a monostable succession of read enabling signals (CPPA, CPPO, CPM) on receiving a predetermined switching edge of an external clock signal (CP). The clock generator enables evaluation of the AND (3) and OR (4) planes of the PLA and subsequently storage of the results through sections (33, 38; 48) duplicating the propagation delays of the signals in the corresponding parts (3-5) of the PLA. Reading is terminated as soon as completion of the storage step is indicated, so that reading of the PLA lasts only as long as strictly necessary, thus preventing erroneous switching while at the same time ensuring correct reading of the PLA.

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