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    42.
    发明专利
    未知

    公开(公告)号：DE69533308T2

    公开(公告)日：2004-11-25

    申请号：DE69533308

    申请日：1995-05-16

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： PULVIRENTI FRANCESCO ,  GARIBOLDI ROBERTO

    IPC: G01R19/165 ,  G01R31/02 ,  G05B19/042 ,  G05B19/05

    Abstract: The invention relates to a method for detecting an open load by means of a driver having at least one main power transistor (M10) connected to the load (L) and one auxiliary transistor (M11) connected in parallel with the main transistor (M10) between a first power supply voltage reference (Vs) and a second voltage reference (GND), the method providing a comparison between a first voltage (VIN1) present on a terminal (S10) connected to the load of the main transistor (M10) and a second voltage (VIN2) present on a terminal (S11) of the auxiliary transistor (M11). The invention also relates to a circuit for detecting an open load (L), in which the said method is implemented.

    43.
    发明专利
    未知

    公开(公告)号：DE69921093D1

    公开(公告)日：2004-11-18

    申请号：DE69921093

    申请日：1999-05-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： D ARRIGO ANGELO ,  CAPICI SALVATORE ,  MARINO FILIPPO ,  PULVIRENTI FRANCESCO

    IPC: H02J7/00 ,  H02M3/156

    Abstract: The frequency translator (72) is usable in a switching DC-DC converter of the type operating as a voltage regulator and as a battery charger. The frequency translator (72) receives at inputs a division voltage (VFB) proportional to a present value of the output voltage (VOUT) of the DC-DC converter (70), a reference voltage (VREF) correlated to a nominal value of the output voltage (VOUT), and a limiting signal (VL) indicative of a normal operation or of current limitation operation of the DC-DC converter (70), and supplies at an output (72u) a bias current (IBIAS) which is supplied to an input of an oscillator (32) supplying at an output a comparison signal (VC) presenting a periodic pattern with a frequency which is correlated to the bias current (IBIAS). In particular, the frequency translator (72) operates in a way such as to regulate a frequency translation of the comparison signal (VC) as a function of the difference between the division voltage (VFB) and the reference voltage (VREF) only when the DC-DC converter (70) is operating in the current limitation condition.

    44.
    发明专利
    未知

    公开(公告)号：ITMI20021426A1

    公开(公告)日：2003-12-29

    申请号：ITMI20021426

    申请日：2002-06-27

    Applicant: ST MICROELECTRONICS SRL ,  DORA SPA

    Inventor： PULVIRENTI FRANCESCO ,  SALA LEONARDO ,  PRIVITERA SALVATORE ,  PAPPALARDO SALVATORE

    IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36

    Abstract: The present invention describes a system for driving rows of a liquid crystal display including at least one module for driving one single row of the liquid crystal display. The module includes an inverter operating in a supply path between a first and a second supply line of the system, where the first supply line includes a first switch for coupling the inverter to a first or to a second supply voltage and the second supply line includes a second switch for coupling the inverter to a third or to a fourth supply voltage. The inverter is driven by logic circuitry and provides a drive signal for one single row of the liquid crystal display.

    45.
    发明专利
    未知

    公开(公告)号：DE69808950T2

    公开(公告)日：2003-12-24

    申请号：DE69808950

    申请日：1998-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIBELLINO CALOGERO ,  MILAZZO PATRIZIA ,  PULVIRENTI FRANCESCO

    IPC: H03K4/02 ,  H03K17/16

    Abstract: Integrated circuit (20, 80, 90) generating at least a voltage linear ramp having a slow rise of the type comprising an input terminal (21, 81, 91), connected to a first voltage reference (VREF) and an output terminal (24, 84, 94) adapted for providing a controlled ramp signal (VRAMP), the circuit comprising at least one operational amplifier (OP3) having a non-inverting input terminal connected to said input terminal (21, 81, 91) and to an output terminal in feedback on an inverting input terminal and connected to the output terminal (24, 84, 94) of the ramp generator circuit (20, 80, 90) itself. The ramp voltage generator (20, 80, 90) according to the invention further comprises a first storage capacitance (Cs) connected between the non-inverting input terminal of the operational amplifier (OP3) and a ground voltage reference (GND) and loaded by means of a second pumping capacitance (Cp) inserted in parallel to said first capacitance (Cs) between the input terminal (21, 81, 91) of the ramp generator circuit (20, 80, 90) and the ground voltage reference (GND).

    47.
    发明专利
    未知

    公开(公告)号：ITMI982003A1

    公开(公告)日：2000-03-14

    申请号：ITMI982003

    申请日：1998-09-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PULVIRENTI FRANCESCO ,  RAVANELLI ENRICO

    IPC: H01L27/02 ,  H01L27/092

    Abstract: The present invention relates to a circuit device for protection against electrostatic discharge, and being immune to the latch-up phenomenon. The circuit device is of the integrated type in a portion of a semiconductor integrated circuit. The device includes an active limiting element and a resistor connected in series between a terminal of the active element connected to an input/output pin of the integrated circuit, and a terminal of a circuit to be protected. The active element is a bipolar transistor having a base terminal and an emitter-acting collector terminal connected together. The distributed resistor is formed in an emitter-acting collector region of the transistor which is diffused and elongated at the surface inside a base pocket of the transistor.

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