公开(公告)号：KR1020080064620A

公开(公告)日：2008-07-09

申请号：KR1020070001711

申请日：2007-01-05

Applicant: 삼성전자주식회사

Inventor： 황용원

IPC: H05K3/46

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09345 ,  Y10T29/4913

Abstract: A printed circuit board is provided to suppress the generation of electromagnetic wave more efficiently by differentiating a signal layer and a ground layer according to a switching speed of a signal to process an electronic element. A printed circuit board(10) includes an external ground layer(11), an insulating material(12), a power layer(13), and at least one signal layer(15). The external ground layer is placed at any one layer among two most external layers. The signal layer is placed at the other layer among the two most external layers. The power layer is formed between the signal layer and the external ground layer. An electronic component having a relatively slow clock signal speed among the mounted electronic components is connected to the external ground layer and an electronic component having a relatively rapid clock signal speed is connected to an intermediate ground layer.

Abstract translation: 提供印刷电路板，通过根据信号的切换速度对信号层和接地层进行微分来更有效地产生电磁波，以处理电子元件。 印刷电路板（10）包括外部接地层（11），绝缘材料（12），功率层（13）和至少一个信号层（15）。 外部地层位于两个最外层之间的任何一层。 信号层位于两个最外层之间的另一层。 功率层形成在信号层和外部接地层之间。 在所安装的电子部件中具有相对慢的时钟信号速度的电子部件连接到外部接地层，并且具有相对较快时钟信号速度的电子部件连接到中间接地层。

公开(公告)号：KR101109239B1

公开(公告)日：2012-01-30

申请号：KR1020090099304

申请日：2009-10-19

Applicant: 삼성전기주식회사

Inventor： 임창현 ,  최석문 ,  김태훈 ,  이영기 ,  신혜숙 ,  손영호

IPC: H05K7/20

CPC classification number: H05K7/205 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/053 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/09345 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2203/0315

Abstract: 본 발명은 방열기판으로, 금속 플레이트; 상기 금속 플레이트의 표면에 형성된 절연막; 상기 절연막 상에 형성된 회로패턴; 및 상기 금속 플레이트를 적어도 일부 관통하여 상기 금속 플레이트와 상기 회로패턴을 전기적으로 연결하는 제1 비아를 포함하여, 방열효과가 뛰어나고 그라운드층과 전원층을 별도로 구비할 필요가 없어 회로기판의 구조가 단순하다.
방열기판, 비아, 전원층, 그라운드층, 알루미늄, 아노다이징 처리

公开(公告)号：KR100669930B1

公开(公告)日：2007-01-17

申请号：KR1020010018943

申请日：2001-04-10

Applicant: 후지쯔 가부시끼가이샤

Inventor： 기쿠치아쯔시 ,  이이지마마코토 ,  이케모토요시히코 ,  모리오카무네하루 ,  기무라요시유키

IPC: H01L23/12

CPC classification number: H05K1/0245 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09345 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/00

Abstract: 본 발명은 전원부와 그라운드부를 기판 내의 각 층에 효율적으로 배치하여, 일반 신호선과 차동 신호선의 양방에 대하여 최적의 임피던스 특성을 달성할 수 있는 다층 배선 기판 및 반도체 장치를 제공하는 것을 과제로 한다.
일반 신호선(1-1, 1-2, 1-3, 1-4)과 차동 신호선(4-1, 4-1)을 다른 면에 배치한다. 차동 신호선이 배치되는 면에 있어서 차동 신호선을 제1영역에 배치하고, 제2영역에 전원 플레인(12-1, 12-3)과 그라운드 플레인 중의 어느 한쪽을 배치한다. 일반 신호선을 제2영역의 수직 방향으로 적층된 상태에서 배치함으로써, 일반 신호선 및 차동 신호선의 양방을 전원 플레인과 그라운드 플레인 사이에 배치한다.
그라운드 플레인, 전원 플레인

Abstract translation: 多层布线基板包括布置在第一电源平面和第一接地平面之间的第一绝缘层内的差动信号线; 以及放置在第二电源平面和第二接地平面之间的第二绝缘层内的一般信号线。 在多层布线基板中，差分信号线被放置在与具有每个通用信号线的平面不同的平面中，使得不同的平面包括具有差分信号线的第一区域，以及具有第二 电源平面和第二个接地层。 通常的信号线以叠层状态放置在第二区域的垂直方向上，使得每条通用信号线都位于第二电源平面和第二接地面之间。

公开(公告)号：WO2005001928A3

公开(公告)日：2005-06-09

申请号：PCT/US2004018091

申请日：2004-06-03

Applicant: INTEL CORP

Inventor： HESTER JENNIFER ,  LI YUAN-LIANG ,  DESMITH MICHAEL ,  FIGUEROA DAVID ,  ZHONG DONG

IPC: H01G4/38 ,  H01L23/498 ,  H01L23/64 ,  H05K1/02 ,  H05K1/11 ,  H04B3/32 ,  H04B3/28 ,  H05K1/16

CPC classification number: H05K1/114 ,  H01G4/385 ,  H01L23/49838 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01057 ,  H01L2924/15312 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2224/0401

Abstract: According to some embodiments, a device includes a first conductive plane electrically coupled to a first terminal associated with a first polarity and a second terminal associated with the first polarity, a second conductive plane electrically coupled to a third terminal associated with a second polarity, and a dielectric disposed between the first conductive plane and the second conductive; plane. A first capacitance is present between the first terminal and the third terminal, a second capacitance is present between the second terminal and the third terminal, and the first capacitance and the second capacitance may be substantially dissimilar.

Abstract translation: 根据一些实施例，一种装置包括电耦合到与第一极性关联的第一端子和与第一极性关联的第二端子的第一导电平面，电耦合到与第二极性关联的第三端子的第二导电平面，以及 布置在所述第一导电平面和所述第二导电之间的电介质; 平面。 在第一端子和第三端子之间存在第一电容，在第二端子和第三端子之间存在第二电容，并且第一电容和第二电容可以基本不相似。

公开(公告)号：WO0225704A3

公开(公告)日：2002-09-06

申请号：PCT/US0129504

申请日：2001-09-20

Applicant: ECOSTAR ELECTRIC DRIVE SYSTEMS LLC ,  PARKHILL SCOTT ,  AYMED SAYEED ,  FLETT FRED

Inventor： PARKHILL SCOTT ,  AYMED SAYEED ,  FLETT FRED

IPC: H01L23/50 ,  H01L23/66 ,  H01L25/07 ,  H05K1/02 ,  H05K1/03 ,  H02M7/00 ,  H05K7/14

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

Abstract translation: 用于电源模块的直流母线具有与负直流导体总线板平行的正直流导体母线板。 一个或多个正极引线连接到正极母线，并且可连接到电源的正极端子。 一个或多个负极引线连接到负母线并且可连接到电源的负极端子。 直流总线具有一个或多个正极连接，可从正极母线固定到电源模块的高侧。 DC总线还具有一个或多个从负母线固定到电源模块的低端的负极连接。 正母线和负母线允许电流逆流，从而消除磁场及其相关的电感，正负母线可连接到电源模块的中心部分。

公开(公告)号：WO0225703A3

公开(公告)日：2002-09-06

申请号：PCT/US0129502

申请日：2001-09-20

Applicant: ECOSTAR ELECTRIC DRIVE SYSTEMS LLC ,  AYMED SAYEED ,  PARKHILL SCOTT ,  FLETT FRED

Inventor： AYMED SAYEED ,  PARKHILL SCOTT ,  FLETT FRED

IPC: H01L23/50 ,  H01L23/66 ,  H01L25/07 ,  H05K1/02 ,  H05K1/03 ,  H02M7/00 ,  H05K7/14

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A DC bus for use in a power module includes a positive DC conductor bus plate parallel with a negative DC conductor bus plate. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

Abstract translation: 用于功率模块的DC总线包括与负DC导体总线板平行的正直流导体母线板。 正母线和负母线允许电流逆流，从而消除磁场及其相关的电感，正负母线可连接到电源模块的中心部分。

公开(公告)号：WO02025732A2

公开(公告)日：2002-03-28

申请号：PCT/US2001/029503

申请日：2001-09-20

IPC: H01L23/50 ,  H01L23/66 ,  H01L25/07 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A high frequency, low impedance network is integrated into the substrate level of a power module for the reduction of electromagnetic interference ("EMI"). In one embodiment, capacitance is electrically connected to at least one of the positive conducting layer in a substrate or the negative conducting layer in a substrate and a ground. Integrating a capacitive network of low stray inductance in a substrate of a power module allows relatively small, inexpensive capacitors to be used.

Abstract translation: 高频，低阻抗网络被集成在功率模块的基板级中，以减少电磁干扰（“EMI”）。 在一个实施例中，电容电连接到衬底中的正导电层中的至少一个或衬底中的负导电层和接地。 将低杂散电感的电容网络集成在功率模块的基板中允许使用相对较小的便宜的电容器。

公开(公告)号：WO02025704A2

公开(公告)日：2002-03-28

申请号：PCT/US2001/029504

申请日：2001-09-20

IPC: H01L23/50 ,  H01L23/66 ,  H01L25/07 ,  H05K1/02 ,  H05K1/03 ,  H01L

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

Abstract translation: 本发明涉及用于电源模块的DC总线。 它由两个平行的扁钢组成，一个正面，另一个负面。 连接到正极条上的一个或多个正导体可以连接到电源的正极。 连接到负极条的一个或多个负极导线可以连接到电源的负极。 直流母线有一个或多个正极连接，可以连接到正极连接杆上，以连接电源模块的高端。 直流母线还有一个或多个负极连接，可以连接到负极连接到达电源模块的底部。 该正棒和负棒总线提供相反的电流，消除磁场和相关电感，并使两个棒连接到电源的中心部分。

公开(公告)号：WO01058224A1

公开(公告)日：2001-08-09

申请号：PCT/NL2001/000057

申请日：2001-01-26

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0231 ,  H05K1/0262 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A printed circuit board intended for mounting at least one integrated circuit (1) and associated decoupling capacitors (21, 22) on the same surface of the printed circuit board. The printed circuit board comprises a stack of alternate conductive and insulating layers (81-87). One of the conductive layers (81) is arranged as a first power plane. The other conductive layers (83, 85, 87) are patterned and provided with signal tracks (831, 851, 871, 872). The stack of layers includes contact holes (91, 92) connected to the first power plane (81), which are arranged for being connected to decoupling capacitors (21, 22). At least one (83) of the patterned conductive layers locally provides at least one second power plane (833) under that part of the aforesaid surface of the printed circuit board which is arranged for mounting an integrated circuit (1) thereon, and furthermore it includes power tracks (832), which form part of connecting means which are arranged for being connected to decoupling capacitors (21, 22) or which make up the connecting means (93, 94). The integrated circuit (1) can be a BGA-type integrated circuit, and the printed circuit board comprising components mounted thereon can be used advantageously in a single-chip cabel modem.

Abstract translation: 用于将至少一个集成电路（1）和相关联的去耦电容器（21,22）安装在印刷电路板的相同表面上的印刷电路板。 印刷电路板包括一叠交替的导电和绝缘层（81-87）。 导电层（81）中的一个被布置为第一电源层。 其他导电层（83,85,87）被图案化并且设置有信号轨迹（831,851,871,872）。 层叠层包括连接到第一电源平面（81）的接触孔（91,92），其被布置成连接到去耦电容器（21,22）。 图案化导电层中的至少一个（83）局部地提供至少一个第二电源平面（833），所述至少一个第二电源平面（833）位于布置用于在其上安装集成电路（1）的印刷电路板的上述表面的该部分之下，此外 包括电源轨道（832），其形成连接装置的一部分，连接装置被布置成连接到去耦电容器（21,22）或构成连接装置（93,94）。 集成电路（1）可以是BGA型集成电路，并且包括安装在其上的部件的印刷电路板可以有利地用于单芯片调制解调器。

公开(公告)号：US20190007259A1

公开(公告)日：2019-01-03

申请号：US16021292

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Stephen Harvey Hall ,  Yun Rou Lim

IPC: H04L29/10 ,  H01R13/66 ,  H05K1/02

CPC classification number: H04L29/10 ,  H01R13/6658 ,  H01R13/6691 ,  H05K1/025 ,  H05K1/0251 ,  H05K2201/09345 ,  H05K2201/09727

Abstract: Apparatus and methods are provided for ameliorating distortion issues associated with a conductor that passes over a void in a reference plane. In an example, the signal conductor can include a first part routed over the major surface of a first side of the reference plane structure on a first side of the void and that approaches a first edge of the reference plane structure with a first trajectory, a second part routed over the major surface of the reference plane structure on a second side of the void and that approaches a second edge of the reference plane structure with a second trajectory, and a third portion connecting the first portion with the second portion, the third portion spanning the void, and having a plurality of spurs extending from a body of the third portion.