公开(公告)号：EP0802569A1

公开(公告)日：1997-10-22

申请号：EP96830212.5

申请日：1996-04-15

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Cappelleti, Paolo

IPC: H01L27/115 ,  G11C16/00

CPC classification number: H01L27/11517 ,  G11C11/005 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.

Abstract translation: 通过EEPROM单元的特殊结构实现了根据低电源电压和低功耗FLASH-EPROM工艺制造的全功能EEPROM存储器块在FLASH-EPROM存储器器件中的成本效益高的集成，从而电容耦合 在单元的浮动栅极和控制栅极之间在与单元的有源区域相邻的场氧化物上实现。 本发明的方法允许对FLASH-EPROM和EEPROM单元的不同隧道和栅极氧化物的厚度以及两个存储器块的外围电路的晶体管的厚度进行优化调制，所述两个存储器块的外围电路预定以相对较低的电源 电压或升压电压。

公开(公告)号：EP0798732A1

公开(公告)日：1997-10-01

申请号：EP96830164.8

申请日：1996-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G11C7/06

CPC classification number: G11C7/065 ,  G11C16/28

Abstract: A gain modulated sense amplifier, particularly for memory devices, that comprises a virtual ground latch structure (2) that has two output nodes (OUT-L, OUT-R) and has the particularity that it comprises an equalization transistor (7) of a first polarity that is adapted to equalize the two output nodes (OUT-L, OUT-R) and is connected between a first branch (8) and a second branch (9), in which the output nodes are arranged; the equalization transistor (7) is driven by an equalization signal (EQ) whose slope can be modulated as a function of the conductivity of the memory cell of the memory device involved in the reading operation.

Abstract translation: 一种增益调制读出放大器，特别是用于存储器件的增益调制读出放大器，其包括具有两个输出节点（OUT-L，OUT-R）的虚拟接地锁存结构（2），并且具有特殊性，它包括均衡晶体管 第一极性，其适于使两个输出节点（OUT-L，OUT-R）均衡，并且连接在其中布置有输出节点的第一分支（8）和第二分支（9）之间; 均衡晶体管（7）由均衡信号（EQ）驱动，均衡信号（EQ）的斜率可以作为读取操作中涉及的存储器件的存储单元的电导率的函数进行调制。

公开(公告)号：EP0798642A1

公开(公告)日：1997-10-01

申请号：EP96830167.1

申请日：1996-03-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi

IPC: G06F11/20

CPC classification number: G11C29/84

Abstract: A redundancy management method, particularly for non-volatile memories, having the particularity of comprising the steps of:

-- enabling, as a consequence of the presence of a pulsed read address transition signal of a memory line, and throughout the duration of the pulsed signal, the memory matrix line reading path, and blocking the selection of redundancy lines of the memory; and
-- at the end of the pulsed signal, as a consequence of the absence/presence of a redundancy line read signal, confirming/disabling the selection of the lines of the memory matrix and blocking/releasing the selection of the redundancy lines.

A redundancy management architecture for a memory matrix, adapted to perform the above method, is also described.

Abstract translation: 冗余管理方法，特别是对于非易失性存储器，具有包括如下步骤的特殊性： - 使作为存储器线的脉冲读地址转换信号的存在的结果，并在整个脉冲的持续时间 信号，存储器矩阵行读取路径，并阻断的存储器的冗余行选择; 和 - 在所述脉冲信号的结束，因为不存在的结果/冗余线的存在的读出信号，确认/禁用存储器矩阵的行的选择和阻断/释放冗余线的选择。 冗余管理体系结构的存储器矩阵，angepasst执行上述方法中，如此描述。

公开(公告)号：EP0797209A1

公开(公告)日：1997-09-24

申请号：EP96830129.1

申请日：1996-03-20

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Fontana, Marco ,  Barcella, Antonio

IPC: G11C7/00

CPC classification number: G11C7/1006

Abstract: A non-volatile memory device, having the particularity that it comprises an internal bus (3) for the transmission of data and other information of the memory to output pads (4); timer means (8); and means (5, 5') for enabling/disabling access to the internal bus; the timer means (8) time the internal bus to transmit information signals of the memory device that originate from local auxiliary lines (7) over the internal bus (3) when the bus is in an inactive period during a normal memory data reading cycle; the timer means (8) drive the enabling/disabling means (5, 5') to allow/deny access to the internal bus (3) on the part of the information signals or of the data from or to the memory.

Abstract translation: 一种非易失性存储器件，其特征在于它包括用于将数据和存储器的其它信息传送到输出焊盘（4）的内部总线（3）。 定时器装置（8）; 以及用于启用/禁用访问所述内部总线的装置（5,5'）; 当总线在正常存储器数据读取周期期间处于非活动期间时，定时器装置（8）使内部总线在内部总线（3）上传送来自本地辅助线（7）的存储器件的信息信号; 定时器装置（8）驱动启用/禁用装置（5,5'）以允许/拒绝部分信息信号或来自或向存储器的数据的内部总线（3）的访问。

公开(公告)号：EP0797165A1

公开(公告)日：1997-09-24

申请号：EP96830137.4

申请日：1996-03-21

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Manganaro, Gabriele ,  Lavorgna, Mario ,  Lo Presti, Matteo ,  Fortuna, Luigi

IPC: G06G7/60

CPC classification number: G06G7/26 ,  G06N3/0635

Abstract: A neural cellular network (10) for implementing a so-called Chua's circuit, and comprising at least first (11), second (12) and third (13) cells having respective first (I111, I121, I131) and second (I112, I122, I132) input terminals and respective state terminals (T11, T12, T13), the first (I111, II121, I131) and second (I112, I122, I132) input terminals being to receive a first (V1) and a second (V2) reference signal, respectively, and the first cell (11), and the second (12) and third (13) cells being of mutually different types.

Abstract translation: 一种用于实现所谓的蔡氏电路的神经细胞网络（10），并且包括至少第一（11），第二（12）和第三（13）小区，其具有相应的第一（I111，I121，I131）和第二（I112， I122，I132）输入端子和各状态端子（T11，T12，T13），第一（I111，II121，I131）和第二（I112，I122，I132）输入端子接收第一（V1）和第二 V2）参考信号，并且第一单元（11）和第二单元（12）和第三单元（13）是相互不同类型的。

公开(公告)号：EP0794609A1

公开(公告)日：1997-09-10

申请号：EP96830103.6

申请日：1996-03-08

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Demicheli, Marco ,  Pisati, Valerio

IPC: H03B1/00 ,  H03L7/099

CPC classification number: H03L7/0805 ,  H03L7/099

Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors.
In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

Abstract translation: 所描述的系统包括各种电路单元（10，11，12），每个具有一个电容器（C0，C1，C2）和用于在所述之间的比率（I / C）定义的量DEPENDING充电装置（G0，G1，G2） 充电电流和电容器的电容。 为了由于在集成电路制造工艺的参数的波动自动为从标称电容的实际电容的偏差进行补偿，该系统具有电路单元的锁相环（PLL），其使用（10）之一 作为可调振荡器，和电流传感器装置（17）从而调节电容器的电路单元的充电电流（C1，C2）（11，12）在根据所述振荡器的电容器的调节充电电流（C0） （10）或者PLL环路的误差电流。

公开(公告)号：EP0794512A1

公开(公告)日：1997-09-10

申请号：EP96830099.6

申请日：1996-03-07

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Mancuso, Massimo ,  Poluzzi, Rinaldo

IPC: G06T5/20 ,  H04N5/21

CPC classification number: H04N5/213 ,  G06T5/20 ,  H04N5/14

Abstract: A processing device for video signals comprising: a memory device (1) suitable to store discrete image elements of a video field; a filtering device (3) supplied by the memory device and suitable to recover errors introduced by the memory device. The filtering device (3) comprises: a filter (4) having an input supplied with digital signals representative of values of a plurality of discrete image elements (P1...P8,X) comprising an image element (X) to be examined and neighbouring image elements (P1...P8), the discrete image elements being stored in the memory device (1), and an output supplying digital signals (CO) representative of a filtered value of the image element to be examined (X); noise detector means (5) operating on fuzzy-logic rules having an input supplied with the digital signals representative of the plurality of values of the image elements (P1...P8,X) and an output supplying a weight signal (K) representative of a degree of erroneousness of the discrete image element to be examined (X), the noise detector circuit (5) determining the degree of erroneousness comparing the value of the image element to be examined (X) with the values of the neighbouring image elements (P1...P8); soft-switch means (7) having a first input supplied with the digital signals representative of the value of the image element to be examined (X), a second input supplied with the output (CO) of the filter (4), a third input supplied with the weight signal (K), and an output supplying digital signals (O) representative of a weighted average of the output of the filter (CO) and of the digital signals representative of the value of the image element to be examined (X) according to respective weights determined by the degree of erroneousness.

Abstract translation: 一种用于视频信号的处理装置，包括：适于存储视频场的离散图像元素的存储器件（1）; 由存储装置提供并适于恢复由存储装置引入的错误的过滤装置（3）。 滤波装置（3）包括：滤波器（4），其具有输入代表包括待检查的图像元素（X）的多个离散图像元素（P1 ... P8，X）的值的数字信号的输入） 相邻图像元素（P1 ... P8），离散图像元素被存储在存储器件（1）中，以及输出提供表示待检查图像元素（X）的滤波值的数字信号（CO）; 噪声检测器装置（5）对具有表示图像元素（P1 ... P8，X）的多个值的数字信号的输入的模糊逻辑规则进行操作，以及提供加权信号（K）代表的输出 （X）的离散图像元素的错误程度，噪声检测器电路（5）确定将要检查的图像元素（X）的值与相邻图像元素的值进行比较的错误程度 （P1，...，P8）; 软开关装置（7）具有提供有表示待检查图像元素（X）的值的数字信号的第一输入，提供有滤波器（4）的输出（CO）的第二输入，第三输入 输入提供有加权信号（K）的输出，以及输出表示滤波器（CO）的输出的加权平均数字和表示待检查图像元素的值的数字信号的数字信号（O） X）根据由错误程度确定的各自的权重。

公开(公告)号：EP0793238A1

公开(公告)日：1997-09-03

申请号：EP96830088.9

申请日：1996-02-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Beverina, Bruno ,  Cappelletti, Paolo ,  Gastaldi, Roberto

IPC: G11C16/06

CPC classification number: G11C16/14 ,  G11C16/12

Abstract: A device incorporating electrically programmable non-volatile memory cells for a small number of programming cycles, in which an individual cell is impressed, both during the write step and the erase step, a bias condition such that a charge flow can only occur between the drain region and the gate dielectric, and vice versa.

Abstract translation: 一种装置，包含电可编程的非易失性存储器单元用于少量编程周期，在其中个体单元印象深刻，在写入步骤和所述擦除步骤中，偏置条件的搜索没有电荷流动只能漏极之间都会出现 区域和栅极电介质，并且反之亦然。

公开(公告)号：EP0400748B1

公开(公告)日：1997-08-20

申请号：EP90201351.5

申请日：1990-05-29

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Taliercio, Michele ,  Lavorgna, Mario ,  Poluzzi, Rinaldo ,  Rizzotto, Gianguido

IPC: G06F17/16

CPC classification number: G06F17/14 ,  G06F17/16

公开(公告)号：EP0788168A1

公开(公告)日：1997-08-06

申请号：EP96830040.0

申请日：1996-01-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l.

Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Alessandri, Mauro

IPC: H01L29/423 ,  H01L21/336 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/66825

Abstract: A process of fabricating a floating-gate memory device, the process including the steps of: forming a stack of superimposed layers including a floating gate region (20), a dielectric region (21), and a control gate region (22); and forming an insulating layer (35) of oxynitride to the side of the floating gate region to completely seal the floating gate region outwards and improve the retention characteristics of the memory device. The insulating layer (35) is formed during reoxidation of the sides of the floating gate region (20), after self-align etching the stack of layers (20-22) and implanting the source/drain of the cell.

Abstract translation: 制造浮动栅极存储器装置的方法，该方法包括以下步骤：形成叠置的层包含一浮动栅极区（20），介电区域（21），和控制栅极区域（22）的堆叠; 以及形成绝缘氧氮化物的层（35）到浮栅区域的一侧完全呼叫向外密封浮栅区，提高了存储装置的保持特性的。 在绝缘层（35）的浮置栅极区域（20）的侧面的再氧化过程中形成，之后自对准蚀刻层的堆叠（20-22）和注入单元的源极/漏极。