中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

152 records (took 0.042 seconds)

    단결정 스타구조 형성방법 및 이를 이용한 3차원 낸드 플래시 메모리 어레이
    51.
    发明公开
    단결정 스타구조 형성방법 및 이를 이용한 3차원 낸드 플래시 메모리 어레이 有权
    单晶硅堆叠阵列的制作方法和使用其的3D NAND闪存存储阵列

    公开(公告)号：KR1020110095676A

    公开(公告)日：2011-08-25

    申请号：KR1020100015280

    申请日：2010-02-19

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  윤장근

    IPC: H01L27/115

    CPC classification number: H01L27/11578 ,  H01L21/28273 ,  H01L27/0688 ,  H01L27/11582

    Abstract: PURPOSE: A method for forming a single crystal STAR(Stacked Array) structure and a three dimensional NAND flash memory array using the same are provided to independently contact each layer through one photolithography process by etching each semiconductor layer of a contact unit with a step shape. CONSTITUTION: A contact unit(116) is formed by vertically laminating a plurality of single crystal semiconductor layers while interposing an insulation layer. A cell forming unit(216) is connected to each single crystal semiconductor layer of the contact unit through two or more lines. The insulation layer is formed between the lines. The plurality of single crystal semiconductor layers is vertically laminated. A plurality of control gates(300) vertically surrounds two or more lines adjacent to a plurality of line selection gates and is horizontally separated while interposing the insulation layer with a charge storage layer. A ground selection gate vertically surrounds two or more lines while interposing the gate insulation layer.

    Abstract translation: 目的：提供用于形成单晶STAR（堆叠阵列）结构的方法和使用其的三维NAND快闪存储器阵列，以通过一个光刻工艺独立地接触每个层，通过蚀刻具有台阶形状的接触单元的每个半导体层 。 构成：通过在插入绝缘层的同时垂直层叠多个单晶半导体层来形成接触单元（116）。 电池形成单元（216）通过两条或多条线路连接到接触单元的每个单晶半导体层。 绝缘层形成在线之间。 多个单晶半导体层被垂直层压。 多个控制栅极（300）垂直地围绕与多个线选择栅极相邻的两条或更多条线，并且在将绝缘层与电荷存储层插入的同时水平分离。 在插入栅极绝缘层的同时，接地选择栅极垂直地包围两条或更多条线。

    일회 프로그램 가능한 비휘발성 메모리 어레이와 그 동작 및 제조방법
    52.
    发明公开
    일회 프로그램 가능한 비휘발성 메모리 어레이와 그 동작 및 제조방법 有权
    一次性可编程非易失性存储器阵列及其操作和制造方法

    公开(公告)号：KR1020110045661A

    公开(公告)日：2011-05-04

    申请号：KR1020090102324

    申请日：2009-10-27

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  조성재 ,  이정훈

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/2463 ,  H01L21/265 ,  H01L27/2409 ,  H01L29/66143

    Abstract: PURPOSE: A one-time programmable nonvolatile memory array and a method for operating and manufacturing the same are provided to perform a reading operation using a PN junction or a Schottky junction, thereby highly integrating a memory array by an existing lithographically process. CONSTITUTION: Bit lines(BL1, BL2) are formed on a semiconductor substrate(12a) by a first semiconductor material. One or more word lines(WL1, WL2, WL3) are formed by a conductive material. A second semiconductor material(16a) is interposed between the bit lines and word lines to form a PN junction with the bit lines. An insulating film(44) is formed between the second semiconductor material and the word lines. The semiconductor substrate and the second semiconductor material are P-type semiconductors.

    Abstract translation: 目的：提供一次性可编程非易失性存储器阵列及其操作和制造方法，以使用PN结或肖特基结进行读取操作，从而通过现有的光刻工艺高度集成存储器阵列。 构成：通过第一半导体材料在半导体衬底（12a）上形成位线（BL1，BL2）。 一个或多个字线（WL1，WL2，WL3）由导电材料形成。 第二半导体材料（16a）插在位线和字线之间以与位线形成PN结。 在第二半导体材料和字线之间形成绝缘膜（44）。 半导体衬底和第二半导体材料是P型半导体。

    기둥형 단결정 채널 및 가상 소스/드레인을 갖는 낸드 플래시 메모리 어레이 및 그 제조방법
    53.
    发明公开
    기둥형 단결정 채널 및 가상 소스/드레인을 갖는 낸드 플래시 메모리 어레이 및 그 제조방법 有权
    具有支柱型单晶通道和虚拟源/漏极及其制造方法的NAND闪存存储阵列

    公开(公告)号：KR1020110037470A

    公开(公告)日：2011-04-13

    申请号：KR1020090094928

    申请日：2009-10-07

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  심원보

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/11578 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11582

    Abstract: PURPOSE: A nand flash memory array having pillar type single crystal channel and a virtual source/drain and fabrication method of the same are provided to simply implement a plurality of gates by repeatedly depositing and etching an insulating film and a conductive film. CONSTITUTION: In a nand flash memory array having pillar type single crystal channel and a virtual source/drain and fabrication method of the same, a column(12) is formed on a substrate(10). A common source area(40) is formed on the substrate between columns to form a first impurity doping layer. A lower selection gate(53) is formed on a common source region and the column while having a first insulating layer(24a) between them. A word line is formed on the lower selection gate and the column. An upper selection gate(75) is formed on a conductive layer(74) and each column while having a third insulating film(67).

    Abstract translation: 目的：提供具有柱型单晶通道的n型闪存阵列及其虚拟源极/漏极及其制造方法，以通过重复沉积和蚀刻绝缘膜和导电膜简单地实现多个栅极。 构成：在具有柱型单晶通道的nand闪存阵列及其虚拟源极/漏极及其制造方法中，在衬底（10）上形成柱（12）。 在列之间的衬底上形成公共源区（40），以形成第一杂质掺杂层。 下部选择栅极（53）形成在公共源极区域和列上，同时在它们之间具有第一绝缘层（24a）。 在下选择门和列上形成字线。 上部选择栅极（75）形成在导电层（74）和每个列上，同时具有第三绝缘膜（67）。

    돌출된 바디를 저장노드로 하는 메모리 셀 및 그 제조방법
    54.
    发明公开
    돌출된 바디를 저장노드로 하는 메모리 셀 및 그 제조방법 有权
    具有存储节点的存储单元和其制造方法

    公开(公告)号：KR1020100130407A

    公开(公告)日：2010-12-13

    申请号：KR1020090049080

    申请日：2009-06-03

    Applicant: 서울대학교산학협력단

    Inventor： 박병국 ,  김가람

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L27/108 ,  H01L21/02225 ,  H01L21/2255 ,  H01L29/41725

    Abstract: PURPOSE: A memory cell having a raised body for a storage node and a fabrication method of the same are provided to prevent SRH recombination by forming a protruded body and performing high doping on one side of the body. CONSTITUTION: A source(24) and a drain(28) are formed on a buried oxide of an SOI substrate and are separated from each other. A body region(26) is interposed between the source and the drain and is higher than them. The body region is protruded to be 1.5-2 times as high as the source and the drain. A gate(42) is formed on at least one side of the body region while having an insulating layer between the gate and the source. Two gates are formed at both ends of the body region and have the insulating layer between the two gates.

    Abstract translation: 目的：提供具有用于存储节点的凸起体的记忆单元及其制造方法，以通过形成突出体并在身体的一侧执行高掺杂来防止SRH复合。 构成：在SOI衬底的掩埋氧化物上形成源极（24）和漏极（28），并且彼此分离。 主体区域（26）插入在源极和漏极之间并且高于它们。 体区域突出为源极和漏极的1.5-2倍。 栅极（42）形成在主体区域的至少一侧上，同时在栅极和源极之间具有绝缘层。 两个门形成在本体区域的两端，并且在两个门之间具有绝缘层。

Patent Agency Ranking