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公开(公告)号：KR100396916B1
公开(公告)日：2003-09-02
申请号：KR1020000077635
申请日：2000-12-18
Applicant: 한국전자통신연구원
IPC: H04L12/775 , H04L12/851 , H04L12/865 , H04L12/933
Abstract: PURPOSE: A packet connection method between input/output ports for a high speed router is provided to attain a high yield by using a packet priority order determination method for allocating ports according to every packets and prevent the poverty without regard to the data type. CONSTITUTION: A plurality of input/output function modules(110,130) performs a connection function of a physical layer and MAC(Media Access Control) layer and also performs a lookup and buffering function for a packet forwarding. A switch function module(120) has a plurality of packet connection priority order determination function module(121), performs a relay function for determining the switching order when a connection to an output port is set and manages the switch fabric connection for switching by a distribution control as each input port. According to the packet connection priority determination method, one packet among the waited packets is selected and connected to the output port.
Abstract translation: 目的：提供高速路由器的输入/输出端口之间的分组连接方法，以通过使用用于根据每个分组分配端口的分组优先级确定方法来获得高收益，并且防止贫困而不考虑数据类型。 组成：多个输入/输出功能模块（110,130）执行物理层和MAC（媒体访问控制）层的连接功能，并且还执行用于分组转发的查找和缓冲功能。 交换功能模块（120）具有多个分组连接优先级顺序确定功能模块（121），当设置到输出端口的连接时执行用于确定切换顺序的中继功能，并且管理用于切换的交换结构连接 分配控制作为每个输入端口。 根据分组连接优先级确定方法，等待分组中的一个分组被选择并连接到输出端口。
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公开(公告)号：KR1020030056286A
公开(公告)日：2003-07-04
申请号：KR1020010086483
申请日：2001-12-28
Applicant: 한국전자통신연구원
IPC: H04L12/26
Abstract: PURPOSE: A network processor having a packet generator for a test inside and a method for testing a packet path using the same are provided to generates packets for the test without complex software procedures, thereby executing a path test of the packets with only network processor. CONSTITUTION: A packet generator(407) for a test is installed between a physical layer interface(401) and a switch interface(403). The packet generator(407) generates packets for a test under the control of a processor for packet processing, so that the packet generator(407) provides the generated packets to the physical layer interface(401) or the switch interface(403). The packet generator(407) generates the packets appropriate for the physical layer interface(401) or the switch interface(403) according to kinds of interfaces to be tested. The processor for packet processing sets up a loop back path for executing the test.
Abstract translation: 目的：提供具有用于测试内部的分组生成器的网络处理器和用于测试使用其的分组路径的方法，以在没有复杂软件过程的情况下生成用于测试的分组，从而仅使用网络处理器来执行分组的路径测试。 构成：用于测试的分组生成器（407）安装在物理层接口（401）和交换机接口（403）之间。 分组生成器（407）在用于分组处理的处理器的控制下生成用于测试的分组，使得分组生成器（407）将生成的分组提供给物理层接口（401）或交换机接口（403）。 分组生成器（407）根据要测试的接口的种类生成适用于物理层接口（401）或交换机接口（403）的分组。 用于分组处理的处理器设置用于执行测试的循环路径。
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公开(公告)号：KR100388491B1
公开(公告)日：2003-06-25
申请号：KR1019990040405
申请日：1999-09-20
Applicant: 한국전자통신연구원
IPC: H04L12/865 , H04L12/867 , H04L12/70
Abstract: PURPOSE: An apparatus for performing a packet scheduling in a packet switch system is provided to switch packets in which HOL(Head Of Line) blocking is not generated, according to priorities, and to switch packets in which the HOL blocking is generated, according to priorities, so as to fairly switch all inputted packets. CONSTITUTION: Queues(411-41n) temporarily store packets having priorities according to the priorities. A register(420) stores packets in which HOL(Head Of Line) blocking is generated, among the packets according to the priorities. A scheduling controller(430) confirms a stored state of the register(420), and outputs the packets having the HOL blocking to a packet switch system according to a confirmed result. A signal coupler(440) transmits the packets transmitted through the queues(411-41n) and packets transmitted from the register(420) to the packet switch system.
Abstract translation: 目的：提供了一种用于在分组交换系统中执行分组调度的设备，用于根据优先级来切换其中不产生HOL（行首）阻塞的分组，并且根据以下切换来切换其中生成HOL阻塞的分组： 优先级，以公平地切换所有输入的分组。 组成：队列（411-41n）根据优先级临时存储具有优先级的数据包。 寄存器（420）根据优先级存储其中生成HOL（行首）阻塞的分组。 调度控制器（430）确认寄存器（420）的存储状态，并根据确认结果将具有HOL阻塞的分组输出到分组交换系统。 信号耦合器（440）将通过队列（411-41n）发送的分组和从寄存器（420）发送的分组发送到分组交换系统。
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公开(公告)号：KR1020030044506A
公开(公告)日：2003-06-09
申请号：KR1020010075275
申请日：2001-11-30
Applicant: 한국전자통신연구원
IPC: H04L12/28
CPC classification number: H04L45/00 , H04L45/54 , H04L45/7453 , H04L45/7457
Abstract: PURPOSE: A device and a method for managing a lookup table of the LPM(Longest Prefix Matching)-based CAM(Content Addressable Memory) and a recording medium thereof are provided to arrange an upper pointer and a lower pointer in each band of data with the same prefix in length, and to prepare a space for added data by moving data only indicated by the upper pointers and the lower pointers of each data band, so as to simply update the lookup table. CONSTITUTION: A CAM(460) includes a lookup table that stores data with a long prefix starting from the lowest address. A pointer storage(420) includes a lower pointer and an upper pointer. The lower pointer memorizes an address of data with the lowest address among data with the same prefix length every band of the data with the same prefix length, and the upper pointer memorizes the next address of an address of data with the highest address among data with the same prefix length. And a table manager(440) records data of an address memorized by the lower pointer of each band in the address memorized by the upper pointer of the each band, for the each band of data with a prefix shorter than the prefix of added data if the data are added in the lookup table of the CAM(460). Also, the table manager(440) records the added data in the address memorized by the upper pointer for the band of data with the same prefix length as the added data, and updates the addresses memorized by the upper pointer and the lower pointer included in the pointer storage(420).
Abstract translation: 目的：提供一种用于管理基于LPM（最长前缀匹配）的CAM（内容可寻址匹配存储器）及其记录介质的查找表的设备和方法，用于在每个数据带中布置上指针和下指针， 长度相同的前缀，并且通过移动仅由每个数据带的上指针和下指针指示的数据来准备添加数据的空间，以便简单地更新查找表。 构成：CAM（460）包括从最低地址开始存储具有长前缀的数据的查找表。 指针存储器（420）包括下指针和上指针。 下指针在具有相同前缀长度的数据的每个频带上存储具有相同前缀长度的数据中具有最低地址的数据的地址，并且上指针存储具有数据中具有最高地址的数据的地址的下一个地址， 相同的前缀长度。 并且表管理器（440）记录由每个频带的上指针存储的地址中由每个频带的下指针存储的地址的数据，对于每个频带数据的前缀短于添加数据的前缀，如果 数据被添加到CAM（460）的查找表中。 此外，表管理器（440）将添加的数据记录在与添加数据相同的前缀长度的数据带的上指针存储的地址中，并且更新由上指针和下指针包含的存储的地址 指针存储器（420）。
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55.发明授权멀티레이어 패킷 스위치 시스템에 있어서 네트웍 프로세싱모듈의 인터페이스 방법 및 이를 위한 멀티레이어 패킷스위치 시스템 失效多层分组交换机系统和多层分组交换机系统中网络处理模块的接口方法
公开(公告)号：KR100363886B1
公开(公告)日：2002-12-11
申请号：KR1019990062377
申请日：1999-12-27
Applicant: 한국전자통신연구원
IPC: H04L12/801 , H04L12/933
Abstract: 본발명은멀티레이어기능을수행하는스위치시스템에있어서라우팅프로토콜과관련된패킷들의처리효율을높일수있는인터페이스방법및 이를위한멀티레이어패킷스위치시스템에관한것이다. 본발명에서는네트웍프로세싱모듈의 CPU에서처리되어야하는데이터들중에서입출력모듈및 스위치패브릭모듈의시스템관련데이터(RMON, 시스템구성, 시스템제어등)와라우팅프로토콜과관련된라우팅데이터(IGMP, ICMP, ARP 등)를분리하여, 시스템관련데이터는기존의방법과같이 CPU 버스를이용하고, 라우팅관련데이터는일반데이터패킷과마찬가지로스위치패브릭모듈을거친후 이더넷(Ethernet) 프로토콜을이용하여인터페이스한다. 이를위해라우팅관련데이터의인터페이스경로를제공하는이더넷콘트롤모듈을포함하는멀티레이어패킷스위치시스템을제공한다. 본발명이제안하는인터페이스방법은네트웍프로세싱모듈이 CPU 버스를통하여시스템관련데이터를엑세스하는동안네트웍프로세싱모듈의 CPU는대기상태로있지않고라우팅관련데이터를처리할수 있다. 따라서종래의네트웍프로세싱모듈의인터페이스방법에서 CPU가시스템관련데이터들을엑세스하는동안라우팅관련데이터들이입출력모듈의포워딩(Forwarding) 기능부에서처리되지않고대기하는시간을없앨수 있어시스템의패킷처리효율을향상시키게된다.
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Patent Agency Ranking
公开(公告)号：KR1020020048498A
公开(公告)日：2002-06-24
申请号：KR1020000077635
申请日：2000-12-18
Applicant: 한국전자통신연구원
IPC: H04L12/775 , H04L12/851 , H04L12/865 , H04L12/933
CPC classification number: H04L45/58 , H04L47/2433 , H04L47/6275 , H04L49/105 , H04L49/1553
Abstract: PURPOSE: A packet connection method between input/output ports for a high speed router is provided to attain a high yield by using a packet priority order determination method for allocating ports according to every packets and prevent the poverty without regard to the data type. CONSTITUTION: A plurality of input/output function modules(110,130) performs a connection function of a physical layer and MAC(Media Access Control) layer and also performs a lookup and buffering function for a packet forwarding. A switch function module(120) has a plurality of packet connection priority order determination function module(121), performs a relay function for determining the switching order when a connection to an output port is set and manages the switch fabric connection for switching by a distribution control as each input port. According to the packet connection priority determination method, one packet among the waited packets is selected and connected to the output port.
Abstract translation: 目的：提供高速路由器的输入/输出端口之间的分组连接方法，通过使用根据每个分组分配端口的分组优先级顺序确定方法来获得高产量，并且不考虑数据类型来防止贫困。 构成：多个输入/输出功能模块（110,130）执行物理层和MAC（媒体访问控制）层的连接功能，并且还执行用于分组转发的查找和缓冲功能。 开关功能模块（120）具有多个分组连接优先级顺序确定功能模块（121），当与输出端口的连接被设置时，执行用于确定切换顺序的中继功能，并管理用于切换的交换结构连接 分配控制作为每个输入端口。 根据分组连接优先级确定方法，选择等待分组中的一个分组并将其连接到输出端口。
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公开(公告)号：KR1019950022352A
公开(公告)日：1995-07-28
申请号：KR1019930026133
申请日：1993-12-01
IPC: H04L7/04
Abstract: 본 발명은 신호지연에 따른 입력클럭과 시스템의 기준클럭 사이에서 발생하는 클럭의 위상차 정렬을 위한 비트 동기 회로에 있어서, 입력클럭과 직렬 데이타 입력받아 직렬데이타인 입력 데이타를 병렬변환하고 입력클럭으로 래치하는 직/병렬 변환부(101), 입력클럭과 기준클럭을 받아들여 제어신호를 출력하는 기준클럭 타이밍 발생부(104), 상기 직/병렬 변환부(101)의 래치된 병렬데이타와 기준클럭 타이밍 발생부(104)의 제어신호를 입력받아 래치된 병렬데이타를 제어신호로 래치시켜 기준클럭에 동기 시키는 래치부(102), 상기 래치부(102)로부터 래치된 병렬데이타와 기준클럭을 입력받아 래치된 병렬데이타를 기준클럭에 의하여 다시 직렬로 변환하는 병/직렬변환부(103)를 포함하여 구성되는 것을 특징으로 하는 클럭의 위상차 정렬을 위한 비트동기 회로에 관한 것으로, 입력클럭과 기준클럭 사이에 발생하는 클럭들간의 위상차를 정렬하기 위하여 입력되는 데이타를 4개의 병렬 신호로 변환하여 데이타의 전송속도를 낮추어줌으로써 고속의 전송데이타를 비트동기 시킬수 있으며, 병렬변환한 만큼의 지터진폭을 흡수할 수 있다. 또한, 본 발명은 적용할 경우 하드웨어의 구성이 간단하고 경제적인면에서 커다란 효과를 볼 수 있다.
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