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    Convert from zoned format to decimal floating point format
    51.
    发明专利
    Convert from zoned format to decimal floating point format 未知

    公开(公告)号：AU2012360181A1

    公开(公告)日：2014-06-05

    申请号：AU2012360181

    申请日：2012-11-13

    Applicant: IBM

    Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES ,  MITRAN MARCEL ,  COPELAND REID

    IPC: G06F9/30

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

    54.
    发明专利
    未知

    公开(公告)号：DE3854937T2

    公开(公告)日：1996-10-17

    申请号：DE3854937

    申请日：1988-10-17

    Applicant: IBM

    Inventor： SCHWARZ ERIC MARK ,  VASSILIADIS STAMATIS

    IPC: G06F7/533 ,  G06F7/483 ,  G06F7/52

    Abstract: A multi-bit overlapped scanning multiplication system assembles modified partial products in a reduced, non-rectangular banded matrix. The rows of the matrix except for the first and last, are extended with bands of encoded extensions of limited length at the right and left ends of the partial product terms. The width of the significant bits of each partial product term is equal to q-1+S-2, where q is the width of the significant bits plus sign of the multiplicand and S is the number of bits which are overlapped scanned. Each partial product term is shifted S-1 bits from adjacent terms and is banded by encoded extensions to the terms. S-1 bits of encode are placed to the right of every terms except the last, the encode being based on the sign of the next partial product term; and S-1 bits of encoded sign extension are placed to the left of every term except the first, which has no sign extension, and last, to the left of which is placed an S bit encode. The bits of negative partial product terms are inverted, and a "hot 1" is encoded in the right extension in the previous row. The first bit of the multiplier is forced to zero so that the first partial product term is always positive or zero. Carry save adder trees are used to reduce each column of the matrix to two terms. When inputs to a carry save adder are known, the logic of the carry save adder is simplified to save chip space.

    55.
    发明专利
    未知

    公开(公告)号：DE3854937D1

    公开(公告)日：1996-03-07

    申请号：DE3854937

    申请日：1988-10-17

    Applicant: IBM

    Inventor： SCHWARZ ERIC MARK ,  VASSILIADIS STAMATIS

    IPC: G06F7/533 ,  G06F7/483 ,  G06F7/52

    Abstract: A multi-bit overlapped scanning multiplication system assembles modified partial products in a reduced, non-rectangular banded matrix. The rows of the matrix except for the first and last, are extended with bands of encoded extensions of limited length at the right and left ends of the partial product terms. The width of the significant bits of each partial product term is equal to q-1+S-2, where q is the width of the significant bits plus sign of the multiplicand and S is the number of bits which are overlapped scanned. Each partial product term is shifted S-1 bits from adjacent terms and is banded by encoded extensions to the terms. S-1 bits of encode are placed to the right of every terms except the last, the encode being based on the sign of the next partial product term; and S-1 bits of encoded sign extension are placed to the left of every term except the first, which has no sign extension, and last, to the left of which is placed an S bit encode. The bits of negative partial product terms are inverted, and a "hot 1" is encoded in the right extension in the previous row. The first bit of the multiplier is forced to zero so that the first partial product term is always positive or zero. Carry save adder trees are used to reduce each column of the matrix to two terms. When inputs to a carry save adder are known, the logic of the carry save adder is simplified to save chip space.

    56.
    发明专利
    未知

    公开(公告)号：DE3853529T2

    公开(公告)日：1995-09-28

    申请号：DE3853529

    申请日：1988-06-21

    Applicant: IBM

    Inventor： SCHWARZ ERIC MARK ,  VASSILIADIS STAMATIS

    IPC: G06F15/16 ,  G06F9/38 ,  G06F15/80 ,  G06F15/78

    Abstract: A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number of instruction streams in a multiple number of pipeline processors. Since instructions associated with a multiple number of instruction streams are being executed simultaneously by a multiple number of pipeline processors, a tracking mechanism is needed for keeping track of the pipe in which each instruction is executing. As a result, a dynamic history table maintains a record of the pipeline processor number in which each incoming instruction is executing, and other characteristics of the instruction. When a particular instruction is received, it is decoded and its type is determined. Each pipeline processor handles a certain category of instructions; the particular instruction is transmitted to the pipeline processor having its corresponding category. However, before transmission, the pipeline processor is checked for completion of its oldest instruction by consulting the dynamic history table. If the table indicates that the oldest instruction in the pipeline processor should complete, execution of the oldest instruction in such processor completes, leaving room for insertion of the particular instruction therein for execution. When the particular instruction is transmitted to its associated pipeline processor, information including the pipe number is stored in the dynamic history table for future reference.

    Vector string search instruction
    58.
    发明专利
    Vector string search instruction 未知

    公开(公告)号：AU2020221962B2

    公开(公告)日：2022-12-01

    申请号：AU2020221962

    申请日：2020-02-11

    Applicant: IBM

    Inventor： LICHTENAU CEDRIC ,  BRADBURY JONATHAN ,  SCHWARZ ERIC MARK ,  FIGULI RAZVAN PETER ,  PAYER STEFAN

    IPC: G06F16/903

    Abstract: An instruction is provided for performing a vector string search. The instruction to be processed is obtained, with the instruction being defined to be a string search instruction to locate occurrence of a substring within a string. The instruction is processed, with the processing including searching the string specified in one operand of the instruction using the substring specified in another operand of the instruction. Based on the searching locating a first full match of the substring within the string, a full match condition indication is returned with position of the first full match in the string, and based on the searching locating only a partial match of the substring at a termination of the string, a partial match condition indication is returned, with the position of the partial match in the string.

    VECTOR FIND ELEMENT NOT EQUAL INSTRUCTION
    59.
    发明专利
    VECTOR FIND ELEMENT NOT EQUAL INSTRUCTION 未知

    公开(公告)号：ZA201407243B

    公开(公告)日：2021-05-26

    申请号：ZA201407243

    申请日：2014-10-06

    Applicant: IBM

    Inventor： BRADBURY JONATHAN DAVID ,  SLEGEL TIMOTHY ,  SCHWARZ ERIC MARK ,  GSCHWIND MICHAEL KARL

    IPC: G06F40/00

    Abstract: Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare.

    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT
    60.
    发明专利
    CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT 未知

    公开(公告)号：CA2852862C

    公开(公告)日：2020-12-15

    申请号：CA2852862

    申请日：2012-11-13

    Applicant: IBM

    Inventor： CARLOUGH STEVEN ,  SCHWARZ ERIC MARK ,  SLEGEL TIMOTHY ,  GAINEY CHARLES ,  MITRAN MARCEL ,  COPELAND REID

    IPC: G06F9/30 ,  G06F9/318

    Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

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