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    Capacitance evaluation circuit e.g. for on-chip capacitance
    52.
    发明专利
    Capacitance evaluation circuit e.g. for on-chip capacitance 未知

    公开(公告)号：DE10010946A1

    公开(公告)日：2001-09-27

    申请号：DE10010946

    申请日：2000-03-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： THEWES ROLAND ,  LINNENBANK CARSTEN ,  KOLLMER UTE ,  SAUTER STEPHAN

    IPC: G01R27/26 ,  G01R31/28 ,  H01L21/66

    Abstract: The capacitance evaluation circuit has a test path (2) connected to one electrode of the capacitance (Cchar) to be evaluated, for application of 2 different potentials (V1,V2), the other electrode of the capacitance coupled to a second test (3) path with 2 parallel measuring paths connected to a common potential (V0), one of which contains a capacitance measuring instrument (1). A pair of potential sources may be coupled to the first test path via respective switch elements (SW1,SW2), with 2 further switch elements (SW3,SW4) for coupling one or other measuring path to the second electrode.

    53.
    发明专利
    未知

    公开(公告)号：DE10010457A1

    公开(公告)日：2001-09-20

    申请号：DE10010457

    申请日：2000-03-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： THEWES ROLAND ,  SCHLOESSER TILL

    IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H03F1/00 ,  H01F10/00

    Abstract: The integrated circuit includes memory cells (MC) with magnetoresistive memory effect. A matrix-shaped memory cell field (1) has bit lines (BL) and word lines (WL). The memory cells are connected between respective bit lines and respective word lines. The bit lines are connected to respective sense amplifiers (2) for reading a data signal from a corresponding memory cell. The sense amplifier comprises a fed-back operational amplifier (3) which supplies an output signal (OUT). A first control input (31) of the operational amplifier is connected with one of the bit liens. A capacitor is connected between a second control input (32) of the operational amplifier and ground (GND).

    58.
    发明专利
    未知

    公开(公告)号：DE50106894D1

    公开(公告)日：2005-09-01

    申请号：DE50106894

    申请日：2001-03-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KOLLMER UTE ,  LINNENBANK CARSTEN ,  SCHAPER ULRICH ,  THEWES ROLAND

    IPC: G01R31/27 ,  G01R31/28 ,  H01L21/66

    Abstract: An apparatus and method for testing a plurality of electrical components that are coupled to one another. Further, an electrical selection unit, coupled to the electrical components to be tested, is provided for selecting at least one electrical component to be tested. A parasitic voltage drop in the testing circuit can be at least partially compensated using a control element coupled to the electrical components to be tested. The invention makes it possible, for testing of electrical components on a wafer over a large distance, i.e., several millimeters, to permit automated compensation of interference influences which occur as a result of the lines coupling or connecting the components to be tested.

    59.
    发明专利
    未知

    公开(公告)号：DE10010888B4

    公开(公告)日：2004-02-12

    申请号：DE10010888

    申请日：2000-03-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： THEWES ROLAND ,  LINNENBANK CARSTEN ,  KOLLMER UTE ,  SAUTER STEPHAN

    IPC: G11C7/06 ,  G11C11/405 ,  G11C11/4091 ,  G01R27/26 ,  G01R31/28 ,  H01L21/66

    Abstract: A circuit configuration for assessing capacitances in a matrix, which has a number of rows with at least one capacitance in at least one dimension, includes a test arm connected to first electrodes of each of the capacitances to be assessed and by which two different potentials can be applied to the first electrodes, a measurement arm connected to second electrodes of each of the capacitances to be assessed and that has a first measurement path and a second measurement path connected to a common potential. The first measurement path has an instrument for assessing the capacitances and the first and second measurement paths can be connected to the second electrodes. The circuit configuration has a drive device that connects each of the capacitances to be assessed individually to the two different potentials.

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