公开(公告)号：WO1996024895A1

公开(公告)日：1996-08-15

申请号：PCT/US1996001516

申请日：1996-02-05

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HAMMOND, Gary, N. ,  KAHN, Kevin, C. ,  ALPERT, Donald, B.

IPC: G06F09/22

CPC classification number: G06F9/3822 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/45533

Abstract: A data processor (104) is described. The data processor (104) is capable of decoding and executing a first instruction (212) of a first instruction set and a second instruction (213-219) in a second instruction set wherein the first instruction (212) and the second instruction (213-219) originate from a single computer program (210, 211). Alternatively, the data processor (104) can also execute a first instruction (212) of a first instruction set in a first instruction set mode, receive a first interruption indication in the first instruction set mode, service the first interruption indication in a second instruction set mode, return to the first instruction set mode, receive a second interruption indication in the first instruction set mode, and service the second interruption indication in the first instruction set mode.

Abstract translation: 描述数据处理器（104）。 数据处理器（104）能够在第一指令集（212）和第二指令（213）中解码和执行第一指令集的第一指令（212）和第二指令集（213-219） -219）来源于单个计算机程序（210,211）。 或者，数据处理器（104）还可以以第一指令集模式执行第一指令集的第一指令（212），以第一指令集模式接收第一中断指示，在第二指令中服务第一中断指示 设置模式，返回到第一指令集模式，在第一指令集模式下接收第二中断指示，并在第一指令集模式下服务第二中断指示。

公开(公告)号：WO1996023320A1

公开(公告)日：1996-08-01

申请号：PCT/US1996000400

申请日：1996-01-11

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MOSLEY, Larry ,  MADRID, Anna ,  NATARAJAN, Siva

IPC: H01L23/02

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48235 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/0243 ,  H05K1/0262 ,  H05K1/0263 ,  H05K3/3431 ,  H05K3/3436 ,  H05K2201/09809 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2201/10969 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A high performance integrated circuit package (10) placed on a printed circuit (PC) board (56) and having a first dielectric layer. On top of this first dielectric layer a metallized die pad (22) and a first metal ring (38a), surrounding this metallized die pad, are positioned. The metallized die pad and the first metal ring electrically couple to the PC board to receive respectively a first power supply signal and a second power supply signal. An integrated circuit die (12) is then affixed to the metallized die pad. This integrated circuit die (12) has a first power supply signal bond pad (28, 30) and a second power supply signal bond pad (33, 34), which respectively are coupled to the metallized die pad and the first metal ring. Consequently, the metallized die pad and the first metal ring operate as a first power supply plane and a second power supply plane coupling the first and second power supply signals coming from the PC board to the first and second power supply signal bond pads on the integrated circuit die.

Abstract translation: 放置在印刷电路板（PC）板（56）上并具有第一电介质层的高性能集成电路封装（10）。 在该第一电介质层的顶部，定位围绕该金属化管芯焊盘的金属化管芯焊盘（22）和第一金属环（38a）。 金属化管芯焊盘和第一金属环电耦合到PC板以分别接收第一电源信号和第二电源信号。 然后将集成电路管芯（12）固定到金属化管芯焊盘。 该集成电路管芯（12）具有分别耦合到金属化管芯焊盘和第一金属环的第一电源信号焊盘（28,30）和第二电源信号焊盘（33,34）。 因此，金属化管芯焊盘和第一金属环作为第一电源平面和第二电源平面工作，第二电源平面将来自PC板的第一和第二电源信号耦合到集成的第一和第二电源信号焊盘上 电路模。

公开(公告)号：WO1996022571A1

公开(公告)日：1996-07-25

申请号：PCT/US1996000506

申请日：1996-01-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HAYEK, George ,  OZTASKIN, Ali, S. ,  LANGENDORF, Brian ,  YOUNG, Bruce

IPC: G06F13/00

CPC classification number: G06F12/0835 ,  G06F13/1684 ,  G06F13/4059

Abstract: An integrated bus bridge and memory controller circuit (16) enables access to a shared memory (18) with high bandwidth data streaming. The bus bridge and memory controller circuit (16) performs a series of snoop ahead transactions over the processor bus (24) during access transactions to the shared memory (18) that originate over the peripheral bus (26) and thereby enables high bandwidth data streaming on the peripheral bus (26). The bus bridge and memory controller circuit (16) may be used in a computer system (10) having a processor (12) and a cache memory (14) coupled to the processor bus (24), and a set of bus agents (20, 22) coupled to the peripheral bus (26). The circuit (16) may include a write buffer (42) for merging write data received over the buses, a peripheral write buffer (46) that stores a snoop done flag, and a peripheral read prefetch buffer (44).

Abstract translation: 集成总线桥接器和存储器控制器电路（16）使得能够访问具有高带宽数据流的共享存储器（18）。 总线桥接器和存储器控制器电路（16）在通过外围总线（26）发起到共享存储器（18）的访问事务期间，通过处理器总线（24）执行一系列前置提前事务，从而实现高带宽数据流 在外围总线（26）上。 总线桥接器和存储器控制器电路（16）可用于具有耦合到处理器总线（24）的处理器（12）和高速缓冲存储器（14）的计算机系统（10）和一组总线代理（20 ，22），其耦合到所述外围总线（26）。 电路（16）可以包括用于合并通过总线接收的写入数据的写入缓冲器（42），存储窥探完成标志的外围写入缓冲器（46）和外围读取预取缓冲器（44）。

公开(公告)号：WO1996020443A1

公开(公告)日：1996-07-04

申请号：PCT/US1995016761

申请日：1995-12-21

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  CHRISTOPHERSON, Mark ,  WELLS, Steven ,  ATWOOD, Greg ,  BAUER, Mark ,  FAZIO, Albert ,  HASBUN, Robert

IPC: G06F11/00

CPC classification number: G11C29/765 ,  G06F11/1036 ,  G06F11/106 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/88 ,  G11C11/5621 ,  G11C29/00

Abstract: A method of utilizing error detecting and correcting circuitry (56) to detect and correct errors which can occur in data stored in multi-bit cell format in a flash EEPROM memory array (23) before those errors can affect the accuracy of data provided by a flash EEPROM memory array.

Abstract translation: 一种利用错误检测和校正电路（56）来检测和校正在闪存EEPROM存储器阵列（23）中以多位单元格式存储的数据中可能出现的错误，然后这些错误可能影响由 闪存EEPROM存储器阵列。

公开(公告)号：WO1996018953A1

公开(公告)日：1996-06-20

申请号：PCT/US1995016105

申请日：1995-12-11

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  KAR, Rabindra, P.

IPC: G06F13/24

CPC classification number: G06F9/542

Abstract: A method and apparatus for CPU (102) cycle stealing on a non-preemptive multi-tasking operating system (122) allowing a first application (118) to preempt other applications (114, 116) which are running concurrently on the operating system (122). The steps taken to perform the CPU (102) cycle stealing include: inserting (1, 2, 4) a hook near a starting address of message-monitoring calls (112), and vectoring the execution path to the first application (118) whenever one of the other applications calls the message-monitoring calls (112), allowing the first application (118) to steal CPU (102) cycles from one of the other applications (114, 116). The vectoring is provided by the hook (1, 2, 4) inserted near the starting address of the message-monitoring calls (112).

Abstract translation: 一种用于CPU（102）在非抢占式多任务操作系统（122）上循环窃取的方法和装置，其允许第一应用（118）抢占在操作系统（122）上同时运行的其他应用（114,116） ）。 执行CPU（102）循环窃取所采取的步骤包括：在消息监视呼叫（112）的起始地址附近插入（1,2,4）钩子，并且每当向所述第一应用程序（118）引导执行路径时 其他应用程序之一调用消息监视呼叫（112），允许第一应用程序（118）从其他应用程序（114,116）中窃取CPU（102）周期。 该向量由插入在消息监视呼叫（112）的起始地址附近的挂钩（1,2,4）提供。

公开(公告)号：WO1996015552A1

公开(公告)日：1996-05-23

申请号：PCT/US1995014681

申请日：1995-11-13

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MOON, Peter, K. ,  SARANGI, Ananda, G. ,  DEETER, Timothy, L.

IPC: H01L23/053

CPC classification number: B26D7/088 ,  B26F3/002 ,  B65C9/1896 ,  B65H35/10 ,  H01L21/76229

Abstract: A method of forming a substantially planar surface over a trench isolation region (33) of a semiconductor substrate (30). Latent active regions (42) are formed within the trench isolation region (33). A dielectric layer (38) is then deposited over the surface of the semiconductor substrate (30). Then, the dielectric layer (38) is polished back to form a planar surface.

Abstract translation: 一种在半导体衬底（30）的沟槽隔离区（33）上形成基本平坦的表面的方法。 潜在有源区（42）形成在沟槽隔离区（33）内。 然后在半导体衬底（30）的表面上沉积电介质层（38）。 然后，电介质层（38）被抛光以形成平面。

公开(公告)号：WO1996015535A1

公开(公告)日：1996-05-23

申请号：PCT/US1995015029

申请日：1995-11-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  KHIEU, Cong, Q.

IPC: G11C07/02

CPC classification number: G11C7/062

Abstract: A sense amplifier (221) for detecting the difference in voltage between two bitlines (113, 115) of a momory circuit. The sense amplifier is comprised of a differential amplifier (201, 203) which is coupled to the two bitlines (113, 115) and generates an output signal based on voltage levels sensed in the bitlines (113, 115). The differential amplifier (201, 203) is coupled to Vcc and ground through an active load (205, 207) and a current source (209) respectively. To address the problem of increased common mode voltage levels found in the bitlines (113, 115), a pair of transistors (223, 225) are connected in parallel across the active load (205, 207) to Vcc and the differential amplifier (202, 203). The gate of one of the transistors is coupled to one of the bitlines (113, 115) and the gate of the other one of the transistors is coupled to the other one of the bitlines (113, 115). With these two transistors (223, 225) coupled in parallel across the load (205, 207) as described, the differential amplifier (201, 203) has increased immunity to elevated common mode levels found in the bitlines (113, 115).

Abstract translation: 一种读出放大器（221），用于检测回路电路的两个位线（113,115）之间的电压差。 读出放大器包括耦合到两个位线（113,115）的差分放大器（201,203），并且基于在位线（113,115）中感测的电压电平产生输出信号。 差分放大器（201,203）分别通过有源负载（205,207）和电流源（209）耦合到Vcc并接地。 为了解决位线（113,115）中增加的共模电压电平的问题，一对晶体管（223,225）跨越有源负载（205,207）并联连接到Vcc并且差分放大器（202,220） ，203）。 晶体管之一的栅极耦合到位线之一（113,115），另一个晶体管的栅极耦合到另一个位线（113,115）。 利用如上所述并联在负载（205,207）上的这两个晶体管（223,225），差分放大器（201,203）具有增加对位线（113,115）中发现的升高的共模电平的抗扰度。

公开(公告)号：WO1996013769A1

公开(公告)日：1996-05-09

申请号：PCT/US1995014242

申请日：1995-10-31

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  KNOLL, Shaun ,  MORRISS, Jeff, Charles ,  CALLAHAN, Shelagh ,  BHATT, Ajay, V. ,  CADAMBI, Sudarshan, Bala

IPC: G06F03/00

CPC classification number: H04L12/40058 ,  G06F12/0661 ,  G06F12/0684 ,  G06F13/385 ,  H04L12/40078

Abstract: Circuitry and complementary logic are provided to a bus controller (14), a number of 1:n bus signal distributor (18), and a number of bus interfaces (22) of a hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support a hierarchical view of the serial bus elements (16), logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.

Abstract translation: 电路和互补逻辑被提供给总线控制器（14），多个1：n总线信号分配器（18）和用于总线控制器的分级串行总线组件的多个总线接口（22），用于动态地检测和 管理串行总线元件的互连拓扑。 串行总线组件用于将多个等时和异步外设串行地连接到计算机系统的系统单元。 这些电路和互补逻辑支持串行总线元件（16）的分层视图，逻辑上将层次划分为多层。 串行总线元件的这种逻辑视图被总线控制器用于检测互连的串行总线元件的存在以及总线代理的功能，即系统单元和互连的外设，以及将地址分配给串行总线 元件和功能，在上电，复位和操作期间，当串行总线元件被热连接到串行总线组件或从串行总线组件分离时。

公开(公告)号：WO1996013037A1

公开(公告)日：1996-05-02

申请号：PCT/US1995013235

申请日：1995-10-18

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  JAVANIFARD, Jahanshir, J. ,  MEISTER, Kimberley, D.

IPC: G11C13/00

CPC classification number: G11C16/30 ,  G11C5/143

Abstract: An integrated circuit having internal power supplies (60A, 240, 245 and 250) includes circuitry (270) for selecting either (Fig. 13A) the external supply voltages or the internal power supplies to supply voltages to the remaining circuitry of the integrated circuit. The integrated circuit comprises voltage detector circuits for detecting the external voltage levels and a control circuit for selecting either the external supply voltages or the internal power supplies in response to the detected external voltages. The integrated circuit may be a flash EEPROM, and the external voltages may be the operating supply voltage VCC and the programming supply voltage VPP.

Abstract translation: 具有内部电源（60A，240,245和250）的集成电路包括用于选择（图13A）外部电源电压或内部电源以向集成电路的剩余电路供应电压的电路（270）。 集成电路包括用于检测外部电压电平的电压检测器电路和用于响应于检测到的外部电压来选择外部电源电压或内部电源的控制电路。 集成电路可以是闪存EEPROM，并且外部电压可以是工作电源电压VCC和编程电源电压VPP。

公开(公告)号：WO1996010840A1

公开(公告)日：1996-04-11

申请号：PCT/US1995011563

申请日：1995-09-13

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  ONG, Tong-Chern ,  TANG, Daniel, N.

IPC: H01L21/8246

CPC classification number: H01L21/7621 ,  H01L21/76216 ,  H01L21/76221 ,  H01L27/105 ,  H01L27/11521

Abstract: A method of forming a memory device with improved isolation between diffusion lines. Parallel, spaced apart thick oxide strips (201) are grown on a substrate. Next, spaced apart, parallel strips (302) having a polysilicon (302a) and nitride (302b) layer, oriented perpendicular to the first strips (201), are formed. The oxide (201) between the second strips is removed, followed by an implantation to form source (402) and drain (401) regions. The nitride layer (302b) on the second strips is removed on those strips between two drain diffusions (401) and an oxidation is performed to form self-aligned thick oxide (602) over the source and drain regions. The strips from which the nitride has been removed are also oxidized, thus providing isolation between adjacent drain lines.

Abstract translation: 一种形成具有改善的扩散线隔离的存储器件的方法。 在衬底上生长平行的间隔开的厚氧化物条（201）。 接下来，形成具有垂直于第一条带（201）定向取向的间隔开的具有多晶硅（302a）和氮化物（302b）层的平行条带（302）。 去除第二条带之间的氧化物（201），随后进行注入以形成源极（402）和漏极（401）区域。 第二条带上的氮化物层（302b）在两个漏极扩散（401）之间的那些条上被去除，并且在源极和漏极区域上进行氧化以形成自对准的厚氧化物（602）。 去除氮化物的条带也被氧化，从而在相邻的排水管线之间提供隔离。