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公开(公告)号:AU2003223595A1
公开(公告)日:2003-11-03
申请号:AU2003223595
申请日:2003-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor: BASS DAVID S , CASTOR DOUGLAS R , MCCLELLAN GEORGE W , LEVI ALAN M , DESAI BINISH , HEPLER EDWARD L , STARSINIC MICHAEL F
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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公开(公告)号:CA2482616A1
公开(公告)日:2003-10-30
申请号:CA2482616
申请日:2003-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor: BASS DAVID S , CASTOR DOUGLAS R , MCCLELLAN GEORGE W , LEVI ALAN M , DESAI BINISH , HEPLER EDWARD L , STARSINIC MICHAEL F
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (303, 307), a composite channel processing block (305, 309) and a chip rate processing block (301, 311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of paramete rs is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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公开(公告)号:NO20034603D0
公开(公告)日:2003-10-14
申请号:NO20034603
申请日:2003-10-14
Applicant: INTERDIGITAL TECH CORP
Inventor: CASTOR DOUGLAS R , MCCLELLAN GEORGE W , MORABITO JOSEPH T
IPC: H03M13/23 , H03M13/27 , H03M13/29 , H04B1/69 , H04B7/155 , H04B7/208 , H04B7/212 , H04B7/216 , H04B7/26 , H04J3/00 , H04J3/02 , H04L1/00 , H04Q11/00 , H04W88/02 , H04W88/08 , H04B
Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping. The bits are directly read from the determined first interleaver buffer addresses and written to the physical channel buffer addresses.
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54.
公开(公告)号:CA2462880A1
公开(公告)日:2002-10-24
申请号:CA2462880
申请日:2002-04-16
Applicant: INTERDIGITAL TECH CORP
Inventor: MORABITO JOSEPH T , MCCLELLAN GEORGE W , CASTOR DOUGLAS R
IPC: H03M13/23 , H03M13/27 , H03M13/29 , H04B1/69 , H04B7/155 , H04B7/208 , H04B7/212 , H04B7/216 , H04B7/26 , H04J3/00 , H04J3/02 , H04L1/00 , H04Q11/00 , H04W88/02 , H04W88/08
Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer (82). The physical channel buffer addresses (84) are determined corresponding to addresses of the bits after rate matching (88), bit scrambling (90), second interleaving (92) and physical channel mapping (94). The bits are directly read (78) from the first interleaver buffer (82) and written to the physical channel buffer (84) using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer (82) from the address of bits in the physical channel buffer (84). The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matchin g (88), reverse bit scrambling (90), reverse second interleaving (92) and reverse physical channel mapping (94). The bits are directly read from the determined first interleaver buffer addresses (82) and written to the physic al channel buffer addresses (84).
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55.
公开(公告)号:CA2619875C
公开(公告)日:2013-11-26
申请号:CA2619875
申请日:2006-08-22
Applicant: INTERDIGITAL TECH CORP
Inventor: CASTOR DOUGLAS R , MARINIER PAUL
Abstract: A method and apparatus for adjusting a channel quality indicator (CQI) feedback period to increase uplink capacity in a wireless communication system are disclosed. The uplink capacity is increased by reducing the uplink interference caused by CQI transmissions. A wireless transmit/receive unit (WTRU) monitors a status of downlink transmissions to the WTRU and sets the CQI feedback period based on the status of the downlink transmissions to the WTRU. A base station monitors uplink and downlink transmission needs. The base station determines the CQI feedback period of at least one WTRU based on the uplink and downlink transmission needs and sends a command to the WTRU to change the CQI feedback period of the WTRU.
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56.
公开(公告)号:DK1389369T3
公开(公告)日:2010-08-30
申请号:DK02762110
申请日:2002-04-16
Applicant: INTERDIGITAL TECH CORP
Inventor: CASTOR DOUGLAS R , MCCLELLAN GEORGE W , MORABITO JOSEPH T
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公开(公告)号:BRPI0513620A
公开(公告)日:2008-05-13
申请号:BRPI0513620
申请日:2005-07-19
Applicant: INTERDIGITAL TECH CORP
Inventor: HACKETT WILLIAM C , DIFAZIO ROBERT A , HEPLER EDWARD L , REZNIK ALEXANDER , CASTOR DOUGLAS R , ZEIRA ARIELA , GAZDA ROBERT G , KAEWELL JOHN DAVID JR
Abstract: A wireless transmit/receive unit (WTRU) for processing code division multiple access (CDMA) signals. The WTRU includes a modem host and a high speed downlink packet access (HSDPA) co-processor, which communicate over a plurality of customizable interfaces. The modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU as a whole such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.
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公开(公告)号:MX2008002526A
公开(公告)日:2008-03-14
申请号:MX2008002526
申请日:2006-08-22
Applicant: INTERDIGITAL TECH CORP
Inventor: MARINIER PAUL , CASTOR DOUGLAS R
Abstract: La presente invencion se refiere a un metodo y aparato para ajustar un periodo de retroalimentacion indicador de calidad de canal (CQI) para incrementar la capacidad de enlace ascendente en un sistema de comunicacion inalambrico. La capacidad de enlace ascendente es incrementada reduciendo la interferencia de enlace causada por las transmisiones del CQI. Una unidad transmisora/receptora inalambrica (WTRU), monitorea un estado de transmisiones de enlace descendente a la WTRU y establece el periodo de retroalimentacion del CQI basado en el estado de transmisiones de enlace descendente a la WTRU. Una estacion base monitorea las transmisiones de el enlace ascendente y enlace descendente necesarias. La estacion base determina el periodo de retroalimentacion del CQI de al menos, una WTRU basado en las transmisiones de enlace ascendente y enlace descendente necesarias y envia una instruccion a la WTRU para cambiar el periodo de retroalimentacion del CQI de la WTRU.
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公开(公告)号:MX2007005402A
公开(公告)日:2007-05-16
申请号:MX2007005402
申请日:2005-10-25
Applicant: INTERDIGITAL TECH CORP
Inventor: PIETRASKI PHILIP J , STERNBERG GREGORY S , CASTOR DOUGLAS R
Abstract: Un metodo y aparato para polarizar adaptablemente un indicador de calidad de canal (CQI) utilizado para ajustar una configuracion de comunicacion entre un transmisor y un receptor en un sistema de comunicacion inalambrico. El receptor envia un CQI y mensajes de acuse de recibo positivo (ACK)/acuse de recibo negativo (NACK) al transmisor. Los mensajes de ACK/NACK indican la ausencia o la presencia de error, respectivamente, en un paquete de datos transmitidos. El CQI se deriva de la relacion de senal a interferencia (SIR) y de los mensajes de ACK/NACK. El transmisor calcula la proporcion de errores en los bloques (BLER) de los paquetes de datos transmitidos con base en los mensajes de ACK/NACK enviados del receptor. El transmisor compara la BLER de los paquetes de datos transmitidos con una BLER objetivo y polariza el CQI con base en la comparacion, con el fin de lograr la BLER objetivo.
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公开(公告)号:MX2007000987A
公开(公告)日:2007-04-10
申请号:MX2007000987
申请日:2005-07-19
Applicant: INTERDIGITAL TECH CORP
Inventor: DIFAZIO ROBERT A , ZEIRA ARIELA , REZNIK ALEXANDER , HEPLER EDWARD L , HACKETT WILLIAM C , KAEWELL JOHN DAVID JR , CASTOR DOUGLAS R , GAZDA ROBERT G
Abstract: Una unidad de transmision/recepcion inalambrica (WTRU) para procesar senales de acceso multiple de division de codigo (CDMA) . La WTRU incluye un modem huesped y un co-procesador de acceso de paquete descendente de alta velocidad (HSDPA), los cuales se comunican sobre una pluralidad de interfases adaptables. El modem huesped opera de acuerdo con los estandares de Liberacion 4 (R4) de proyecto asociado de tercera generacion (3GPP), y el co-procesador HSDPA mejora las capacidades de comunicacion inalambrica de la WTRU como un total de tal forma que la WTRU opera de acuerdo con los estandares de Liberacion 5 (R5) 3GPP.994.
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