公开(公告)号：WO1982001164A1

公开(公告)日：1982-04-15

申请号：PCT/US1981001310

申请日：1981-09-25

Applicant: NCR CORP

Inventor： NCR CORP ,  KENYON K

IPC: B41J03/12

CPC classification number: G06F17/214 ,  G06K15/10 ,  G09G5/227

Abstract: Format control apparatus enables the printing or display of characters with selectively controllable spacing. Data which represents characters is stored in a buffer store (42) and applied to address a character generator (50) which provides the relevant dot row information of the characters under the control of a row counter (62). The output of the character generator (50) is supplied in parallel to a first shift register (64) which is controlled by a clock divider circuit (54). A serial output from the first shift register (64) is applied to a second shift register (66) coupled to a label (68) which supplies data in a group of parallel bits adapted to a utilization device for the formatted character information. The row counter (62) and clock divider circuit (54) are settable under the control of a mode control circuit (48) to enable the formatting of selectively spaced characters. The character generator (50) may store a plurality of selectable character fonts. A settable character counter (46) controls the number of characters in a line of characters.

Abstract translation: 格式控制装置能够以可选择地间隔的间隔打印或显示字符。 表示字符的数据被存储在缓冲存储器（42）中，并被应用于寻址在行计数器（62）的控制下提供字符的相关点行信息的字符发生器（50）。 字符发生器（50）的输出与由时钟分频器电路（54）控制的第一移位寄存器（64）并联提供。 来自第一移位寄存器（64）的串行输出被施加到耦合到标签（68）的第二移位寄存器（66），标签（68）提供适于格式化字符信息的适用于利用装置的并行比特组中的数据。 行计数器（62）和时钟分频器电路（54）可在模式控制电路（48）的控制下进行设置，以使得能够格式化选择性间隔的字符。 字符发生器（50）可以存储多个可选字符字体。 可设置的字符计数器（46）控制字符行中的字符数。

公开(公告)号：WO1982000730A1

公开(公告)日：1982-03-04

申请号：PCT/US1981001026

申请日：1981-07-30

Applicant: NCR CORP

Inventor： NCR CORP ,  SKAGGS W ,  CURRY J

IPC: G09G03/28

CPC classification number: G09G3/296 ,  G09G3/294

Abstract: In a control system (10) for a plasma display panel (12) having a cell (14a-14i) formed at the cross-over point of each of the panel's column and segment electrodes (C u, C u, C u and S u, S u, S u) AC drive signals having positive and negative components are simultaneously applied to the column and segment electrodes (C u, C u, C u and S u, S u, S u) associated with a designated cell (14a-14i) of the panel (12). These drive signals are 180` out-of-phase and are arranged to produce across the designated cell a voltage swing of sufficient magnitude to produce a discharge therein. In one embodiment of the drive scheme, the positive and negative components of each drive signal are equal. In a second embodiment of the drive scheme, the positive and negative components of each drive signal are not equal. The control system (10) includes a DC-to-AC convertor for producing the AC drive signals, a driver circuit (20a, 20b, 20c) associated with each column electrode (C u, C u, C u) of the display panel and a driver circuit (18a, 18b, 18c) associated with each segment electrode (S u, S u, S u) of the display panel. Each of the column and segment driver circuits is operable to provide to its associated column or segment electrodes both of the components of its associated AC drive signal if it is selected or only one of the components of its associated drive signal it is not selected. In this way, the positive and negative components of the AC drive signals are selectively applied to the panel's column and segment electrodes to produce a desired illumination pattern.

Abstract translation: 在用于等离子体显示面板（12）的控制系统（10）中，具有形成在每个面板的列和分段电极（C u，C u）的交叉点处的单元（14a-14i） u，u，u u，u u，u u，u u u）具有正和负分量的AC驱动信号同时施加到列和段电极（C u， （u，u，u，u，u）与面板（12）的指定单元（14a-14i）相关联。 这些驱动信号是180°异相的，并且被布置成在指定的单元上产生足够大的电压摆幅以在其中产生放电。 在驱动方案的一个实施例中，每个驱动信号的正和负分量相等。 在驱动方案的第二实施例中，每个驱动信号的正和负分量不相等。 控制系统（10）包括用于产生AC驱动信号的DC-AC转换器，与每个列电极（C u，C u，C）相关的驱动电路（20a，20b，20c） 和与显示面板的每个分段电极（S u，S u，u u））相关联的驱动器电路（18a，18b，18c）。 列和段驱动器电路中的每一个可操作以提供其相关联的列或分段电极其相关联的AC驱动信号的两个组件，如果它被选择，或仅其相关联的驱动信号的组件中的一个未被选择。 以这种方式，交流驱动信号的正和负分量被选择性地施加到面板的列和分段电极以产生期望的照明图案。

公开(公告)号：WO1982000220A1

公开(公告)日：1982-01-21

申请号：PCT/US1981000894

申请日：1981-06-29

Applicant: NCR CORP

Inventor： NCR CORP ,  HALL S

IPC: H01J17/04

CPC classification number: H01J11/12 ,  H01J2211/225

Abstract: An electrode structure suitable for use as an input or erase electrode (I or E) in a charge transfer type gas discharge display device (20) includes a conductive base (13 or 16), a layer consisting essentially of a low conductivity metal oxide layer (14 or 17) such as ruthenium oxide, and a thin coating of magnesium oxide dielectric (12) which improves performance of the device (20) but maintains the electrode essentially directly coupled to the ionizable gas in the device (20). The metal oxide layer (14 or 17) serves to protect the thin magnesium oxide dielectric coating (12) from contamination.

Abstract translation: 适合用作电荷转移型气体放电显示装置（20）中的输入或擦除电极（I或E）的电极结构包括导电基底（13或16），基本上由低导电性金属氧化物层 （14或17），例如氧化钌和氧化镁电介质（12）的薄涂层，其改善了器件（20）的性能，但是将电极基本上直接耦合到器件（20）中的可电离气体。 金属氧化物层（14或17）用于保护薄氧化镁介电涂层（12）免受污染。

公开(公告)号：WO1981003389A1

公开(公告)日：1981-11-26

申请号：PCT/US1981000579

申请日：1981-04-30

Applicant: NCR CORP

Inventor： NCR CORP ,  FRANCO G ,  WILDEY T ,  CHRISTENSEN G

IPC: G06F03/00

CPC classification number: G06F3/0489

Abstract: A teleprinter terminal (10) includes a keyboard (70), a thermal printer (62) and communications electronics (44, 56, 58), each of which is operated by means of a self-contained microprocessor (40, 52, 60) which can store and release data, in order to provide a simple and reliable control system for the terminal. The three microprocessors (40, 52, 60) are interconnected by four bit buses (PRINT DATA, TRANSMIT DATA/STATUS) for data transfer operations between the processors which are done in bytes but the four-bit buses forces the bytes to be transferred in two, four-bit exchanges. One four-bit bus (PRINT DATA) is used to connect the communications processor (52) and the keyboard processor (40) with the printer processor (60) for transfer of data to the printer and a second four-bit bus (TRANSMIT DATA/STATUS) is used to connect the keyboard processor and the communications processor for transfer of data to the communications electronics. The communications electronics includes a serial communications interface (44, 58) for data transmission and reception and a parallel interface (56) for data reception only.

公开(公告)号：WO1981002214A1

公开(公告)日：1981-08-06

申请号：PCT/US1981000052

申请日：1981-01-14

Applicant: NCR CORP

Inventor： NCR CORP ,  PELKEY B ,  REAGAN M

IPC: G09G03/10

CPC classification number: G09G3/10

Abstract: A driving circuit for a gas-discharge display device (20) includes a pair of switching members (94, 144) and the secondary windings (92) of a transformer (118) wired in series with one of the switching members. The switching members in response to receiving out-of-phase control signals alternately apply a low voltage pulse to the display device. The secondary windings of the transformer output continuously a high voltage pulse in phase with one of the switching members. Upon the generation of appropriate control signals enabling the operation of the switching members, a voltage of sufficient magnitude is applied to selected cell segments in the display device to fire the cells. The transformer together with the low voltage pulses are driven by a high frequency clock to provide a high intensity display operation.

公开(公告)号：WO1981001893A1

公开(公告)日：1981-07-09

申请号：PCT/US1980001663

申请日：1980-12-09

Applicant: NCR CORP

Inventor： NCR CORP ,  KOCOL J ,  SCHUCK D

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A self-correcting memory system (10) includes internal error detection and correction circuitry (20) that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system (10). The error detection and correction circuitry (20) includes an ECC checking circuit (36) that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter (44) is cascaded to a refresh address counter (42) in the control circuitry (41) of the memory system (10) so that the accessing of each data word occurs during a refresh cycle of the memory system (10).

公开(公告)号：WO1981001768A1

公开(公告)日：1981-06-25

申请号：PCT/US1980001664

申请日：1980-12-09

Applicant: NCR CORP

Inventor： NCR CORP ,  ELLSWORTH W

IPC: G11C19/08

CPC classification number: G11C29/86 ,  G06F11/1032 ,  G11C19/0875

Abstract: A magnetic bubble domain memory device that includes a magnetic domain data chip having a major-minor (20, 26) loop organization with on-chip firmware providing redundancy information enabling the use of the chip even though one or more defective minor loops may be present thereon. One of the pages (68) is written in the minor loop (26), where a page is defined as a common bit position in each of the plurality of minor loops, with a series of magnetic domains having an odd total number. The next succeeding page (70) in the minor loops contains a series of magnetic domains and voids which are representative of the loop numbers of defective minor loops on the chip with the remaining pages (72) in the minor loop having an even number of magnetic domains contained in each of the pages. Collectively, the pages containing the odd and even number of magnetic domains together with the page containing the map of the defective minor loops comprise the on-chip firmware providing redundancy information. This magnetic domain structure is capable of screening out defective minor loops in the read and write operation, and enables synchronization of the magnetic domain device such that a selected page of data may be readily accessed from a plurality of minor loops when desired.

公开(公告)号：WO1981000790A1

公开(公告)日：1981-03-19

申请号：PCT/US1980001179

申请日：1980-09-11

Applicant: NCR CORP

Inventor： NCR CORP ,  TRUDEL M ,  DHAM V

IPC: H01L27/12

CPC classification number: H01L29/66833 ,  H01L29/792

Abstract: A non-volatile memory device includes a semiconductor substrate (16), a thin, 10-15 Angstroms thick, memory oxide layer (11), a silicon nitride layer (12), a 70-100 Angstroms thick interfacial oxide layer (13), and a polysilicon gate electrode (14). The interfacial oxide layer (13) is formed by chemical vapor deposition at a temperature in the range of about 600-625`C.

Abstract translation: 非易失性存储器件包括半导体衬底（16），薄的10-15埃厚的存储氧化层（11），氮化硅层（12），70-100埃厚的界面氧化物层（13） ，和多晶硅栅电极（14）。 界面氧化物层（13）通过化学气相沉积在约600-625℃范围内的温度下形成。

公开(公告)号：WO1980002759A1

公开(公告)日：1980-12-11

申请号：PCT/US1980000665

申请日：1980-05-29

Applicant: NCR CORP

Inventor： NCR CORP ,  NASEEM S ,  AMACHER G ,  BLANFORD D

IPC: G06K07/10

CPC classification number: G06K7/0166

Abstract: A symbol decoding system incorporated in a plurality of NMOS/LSI chips (22, 24, 28, 30) generates data representing numerical characters encoded in the symbol. Scanning means (20) generates signals (RTV, STV) in response to the scanning of a plurality of bars and spaces, which signals are decoded by a first chip (24) as valid and invalid characters, the valid characters being recognized by a second chip (28) which stores the valid characters and enables a microprocessor chip (30) to receive the valid characters assembled as part of the symbol for processing thereof. Logic circuits enable test numerical characters to be generated in response to test signals outputted by the microprocessor chip (30).

公开(公告)号：WO1980002614A1

公开(公告)日：1980-11-27

申请号：PCT/US1980000542

申请日：1980-05-07

Applicant: NCR CORP

Inventor： NCR CORP ,  SCULLEY G ,  PASSER B

IPC: G06K07/10

CPC classification number: G06K7/0163

Abstract: A transition code sensing system includes a record member (32) on which is located a plurality of bar code symbols (34), each of which comprises a data channel (20) and a clocking channel (22). The record member is inserted into a data terminal device and intermittently driven through a printing station in which a sensing member (36) senses the data channel out of phase with the sensing of the clocking channel and generates signals in response thereto. A circuit coupled to the sensing member will process the generated signals and transmit the processed signals to a utilization device. Upon processing the signals representing the last bar code symbol (29) on the record member, the circuit will generate a control signal (88) for stopping the movement of the record member through the printing station, thereby conditioning the record member for a subsequent printing operation.