公开(公告)号：FR3030113A1

公开(公告)日：2016-06-17

申请号：FR1462456

申请日：2014-12-15

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  ST MICROELECTRONICS SA

Inventor： AHMED NAYERA ,  MARTY MICHEL

IPC: H01L27/146

Abstract: L'invention concerne un capteur d'image comprenant une couche semi conductrice (1) ; un empilement (3) de couches isolantes (51, 53, 55) reposant sur la face arrière (F1) de la couche semiconductrice ; une portion de couche conductrice (59) s'étendant sur une partie de la hauteur de l'empilement (3) et affleurant au niveau de la surface exposée de l'empilement ; des doigts conducteurs isolés latéralement (57) s'étendant à travers la couche semiconductrice (1) à partir de sa face avant (F2) et pénétrant dans ladite portion de couche (59) ; des murs conducteurs isolés latéralement (25) séparant des zones de pixel, ces murs s'étendant à travers la couche semiconductrice (1) à partir de sa face avant (F2) et étant moins hauts que les doigts (57) ; et une structure d'interconnexion (5) reposant sur la face avant (F2) de la couche semiconductrice (1) et comportant des vias (13) en contact avec les doigts (57).

公开(公告)号：FR3018954A1

公开(公告)日：2015-09-25

申请号：FR1452334

申请日：2014-03-20

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： FREY LAURENT ,  MARTY MICHEL

IPC: H01L31/0232

Abstract: L'invention concerne un procédé d'optimisation du rendement quantique d'une photodiode dont la partie active (29) est formée dans un substrat en silicium (1) et est recouverte d'un empilement de couches isolantes comprenant successivement au moins une première couche (9) d'oxyde de silicium d'épaisseur comprise entre 5 et 50 nm, une couche antireflet (11) d'épaisseur comprise entre 10 et 80 nm, et une deuxième couche (31) d'oxyde de silicium, le procédé d'optimisation comprenant les étapes suivantes : déterminer pour une longueur d'onde infrarouge des premières épaisseurs (el, e2, e3, e4 ... e8) de la deuxième couche (31) correspondant à des maxima d'absorption (M1, M2, M3, M4 ... M8) de la photodiode, et choisir, parmi les premières épaisseurs, une épaisseur désirée, eoxD, pour que la dispersion maximale de fabrication soit inférieure à la moitié de la pseudo-période séparant deux maxima successifs.

公开(公告)号：FR2881273A1

公开(公告)日：2006-07-28

申请号：FR0500674

申请日：2005-01-21

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  AVENIER GREGORY

IPC: H01L21/762 ,  H01L21/84

Abstract: L'invention concerne un substrat semi-conducteur de circuit intégré comprenant une couche active de silicium (10) séparée d'une couche substrat de silicium (20) par une couche de matériau isolant enterrée (30), caractérisé en ce que ladite couche active de silicium comprend localement au moins une surépaisseur du côté de ladite couche enterrée (30), de sorte que ledit substrat semi-conducteur comprend un état de surface plan.

公开(公告)号：FR2835652B1

公开(公告)日：2005-04-15

申请号：FR0201305

申请日：2002-02-04

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CHANTRE ALAIN

IPC: H01L21/8249

Abstract: When the fabrication of the insulated gate field effect transistor is started, then the bipolar transistor (BIP1,BIP2) is totally fabricated, before the resumption of fabrication of the insulated gate field effect transistor (MOS), and the step of common finishing of the two transistors is executed, including the common thermal reheating treatment (122) and common silication treatment.

公开(公告)号：FR2848724A1

公开(公告)日：2004-06-18

申请号：FR0215837

申请日：2002-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  LEVERD FRANCOIS ,  CORONEL PHILIPPE

IPC: H01L21/68 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L27/12 ,  H01L23/535

Abstract: The production of connections buried in an integrated circuit comprises: (a) providing a structure made up of a first support slice stuck in the rear surface of a thin semiconductor slice, one or more integrated circuit elements possibly being realised in or above the thin slice; (b) sticking a second support slice on the structure at the side of the leading surface of the thin slice; (c) eliminating the first support slice; (d) forming some connections between the different zones of the rear surface of the thin slice; (e) sticking a third support slice on the connections; and (f) eliminating the second support slice. An Independent claim is also included for an integrated circuit incorporating some components and produced by the above process.

公开(公告)号：FR2811473B1

公开(公告)日：2003-09-05

申请号：FR0008686

申请日：2000-07-04

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  BAUDRY HELENE ,  LEVERD FRANCOIS

IPC: H01L21/316 ,  H01L21/762 ,  H01L21/763 ,  H01L21/331 ,  H01L21/306

Abstract: Prior to the implementation of transistors, one configures within the substrate a deep insulated drain following the configuration within the substrate of a less deep insulated drain lengthening the deep drain. The configuration of the deep drain includes a coating of the internal walls of the drain by an initial layer of oxide (100) obtained by a rapid thermal oxidation and a filling of the drain with polysilicon (120) inside an envelope formed with an insulating material (101). The configuration of the less deep drain also includes a coating of the internal walls with an initial oxide layer (15) obtained by rapid thermal oxidation and a filling with an insulating material (16, 17). An Independent claim is also included for an integrated circuit incorporating within a substrate some insulating deep drain and less deep drain regions separating the transistors.

公开(公告)号：DE69808190D1

公开(公告)日：2002-10-31

申请号：DE69808190

申请日：1998-07-03

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： JAOUEN HERVE ,  MARTY MICHEL

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/10 ,  H01L29/92 ,  H01L21/3205

Abstract: Production of a metal-metal capacitor within an IC is carried out by forming the two metal electrodes (40, 71) and the dielectric layer (61) on the lower insulating layer (2) bearing a metallisation level (M1) of the IC before depositing the upper insulating layer (80) for covering the metallisation level (M1). Also claimed is an IC including a metal-metal capacitor (40, 61, 71) produced as described above. Preferably, the first capacitor electrode (40) is part of the metallisation level (preferably aluminium), the second electrode (70, 71) is a thinner layer preferably of aluminium or tungsten and the dielectric layer (61) is a thin SiO2, Si3N4 or Ta2O5 layer.

公开(公告)号：FR2803091A1

公开(公告)日：2001-06-29

申请号：FR9916283

申请日：1999-12-22

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  FELLOUS CYRIL

IPC: H01L21/223 ,  H01L21/331 ,  H01L21/8222

Abstract: Doping of the extrinsic base of a bipolar transistor is effected in the vapor phase by putting into hot contact the region of the extrinsic base (8) with a flow of doping gas (FLX).

公开(公告)号：FR2801420A1

公开(公告)日：2001-05-25

申请号：FR9914746

申请日：1999-11-23

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L29/732

Abstract: Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector on a layer of extrinsic collector in a semiconductor substrate; (b) making a lateral isolating region; (c) making a base next to he intrinsic collector and the lateral isolating region; and (d) making a bipartite dope emitter in situ. Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector (4) on a layer of extrinsic collector (2) in a semiconductor substrate (1); (b) making a lateral isolating region (5) surrounding the upper part of the intrinsic collector and of wells of the imprisoned extrinsic collector (60); (c) making a base (8) next to he intrinsic collector and the lateral isolating region and comprising a non-selective epitaxy of a semiconductor region (8) comprising at least one layer of silicon; (d) making a bipartite dope emitter (11) in situ comprising: (i) making a first layer (110) of the emitter formed from microcrystalline silicon and directly in contact with a part (800) of the upper surface of the semiconductor region situated on top of the intrinsic collector; and (ii) making a second part (111) of emitter from polycrystalline silicon; the two parts (110, 111) being separated by an oxide layer (112).

公开(公告)号：FR2766294B1

公开(公告)日：2001-01-19

申请号：FR9709164

申请日：1997-07-18

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  JAOUEN HERVE

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L27/10 ,  H01L29/92 ,  H01L23/522

Abstract: Production of a metal-metal capacitor within an IC is carried out by forming the two metal electrodes (40, 71) and the dielectric layer (61) on the lower insulating layer (2) bearing a metallisation level (M1) of the IC before depositing the upper insulating layer (80) for covering the metallisation level (M1). Also claimed is an IC including a metal-metal capacitor (40, 61, 71) produced as described above. Preferably, the first capacitor electrode (40) is part of the metallisation level (preferably aluminium), the second electrode (70, 71) is a thinner layer preferably of aluminium or tungsten and the dielectric layer (61) is a thin SiO2, Si3N4 or Ta2O5 layer.