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    51.
    发明专利
    未知

    公开(公告)号：DE69833178D1

    公开(公告)日：2006-04-06

    申请号：DE69833178

    申请日：1998-10-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  CANEGALLO ROBERTO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C27/00 ,  G11C11/56 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34

    Abstract: The reading device (1) comprises an A/D converter (8) of n+m bits receiving an input signal (V1) correlated to the threshold voltage (VTH) of the memory cell (2), and supplying a binary output word (WT) of n+m bits. The A/D converter (8) is of a double conversion stage type (8), wherein a first A/D conversion stage (10) carries out a first analog/digital conversion of the input signal (V1), to supply at the output a first intermediate binary word (W1) of n bits, and the second A/D conversion stage (16) can be activated selectively to carry out a second analog/digital conversion of a difference signal (VD) correlated to the difference between the input signal (V1) and the value of the first intermediate binary word (W1). The second A/D conversion stage (16) generates at the output a second intermediate binary word (W2) of m bits supplied, with the first intermediate binary word (W1), to an adder (20) generating the binary output word (WT) of n+m bits.

    52.
    发明专利
    未知

    公开(公告)号：DE69723700D1

    公开(公告)日：2003-08-28

    申请号：DE69723700

    申请日：1997-11-03

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  CANEGALLO ROBERTO ,  GERNA DANILO ,  CHIOFFI ERNESTINA

    IPC: G11C11/56 ,  G11C27/00

    Abstract: The programming method comprises the steps of: a) determining (140) a current value (Veff) of the threshold voltage (Vth); b) acquiring (100) a target value (Vp) of the threshold voltage; c) calculating (150) a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying (160) a second number (N2) of consecutive voltage pulses to the gate terminal of the cell, said second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring (170) a current value (Veff) of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.

    54.
    发明专利
    未知

    公开(公告)号：IT1313197B1

    公开(公告)日：2002-06-17

    申请号：ITMI991616

    申请日：1999-07-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C11/56

    Abstract: A method for storing n bytes in multi-level non-volatile memory cells, including writing and reading of said n bytes. Writing includes the following steps: (a) decomposing each one of such n bytes into eight bits, (b) storing each one of such eight bits into a respective one of such multi-level non-volatile memory cells by utilizing a multi-level technology. Reading includes the following steps: (c) reading contemporaneously each one of such eight bits which belong to each one of said n bytes by sense amplifiers each connected to each one of such multi-level non-volatile memory cells, (d) assembling such eight bits previously read to form each one of such initial n bytes.

    55.
    发明专利
    未知

    公开(公告)号：IT1312212B1

    公开(公告)日：2002-04-09

    申请号：ITMI990859

    申请日：1999-04-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C16/16

    Abstract: A method for erasing non volatile memories, in particular flash cells, that includes applying erasing pulses to the cells to be erased and to verify, after each pulse, the value of the threshold voltage of the cells. The erasing pulses are provided to the cells as long as the respective values of the threshold voltage are greater than the new values of threshold voltage corresponding to new data to be rewritten in the cells to be erased.

    57.
    发明专利
    未知

    公开(公告)号：IT1305181B1

    公开(公告)日：2001-04-10

    申请号：ITTO980961

    申请日：1998-11-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CANEGALLO ROBERTO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C16/12

    Abstract: The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.

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