公开(公告)号：FR2830365B1

公开(公告)日：2004-12-24

申请号：FR0112519

申请日：2001-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  MAZOYER PASCALE ,  FAZAN PIERRE

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

公开(公告)号：DE60102037T2

公开(公告)日：2004-12-09

申请号：DE60102037

申请日：2001-06-14

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/4094

公开(公告)号：FR2784782B1

公开(公告)日：2003-12-12

申请号：FR9813170

申请日：1998-10-16

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C11/404 ,  G11C11/40

公开(公告)号：DE69907600D1

公开(公告)日：2003-06-12

申请号：DE69907600

申请日：1999-10-21

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： JAOUEN HERVE ,  FERRANT RICHARD

IPC: G11C11/401 ,  H01L21/8242 ,  H01L27/108

Abstract: The cell memory of dynamic random access type comprises a MOS (metal-oxide-silicon) transistor and a capacitor in monolithic structure with the second electrode (311) common to all cells of the same row covered with an insulating layer (312), and comprising independent conducting elements (313-1,313-2) mutually spaced in the same horizontal plane and alternatively high and low polarized. The low potential is the reference potential of the memory circuit equal to e.g. that of the ground. The high potential is the writing potential equal to e.g. the supply potential Vdd. The second electrode (311) is made up of a metallic layer of e.g. tungsten, and a conducting layer of e.g. polycrystalline silicon. The insulating layer (312) is of e.g. silicon oxide. The equivalent capacitance of the memory circuit is in the form of three decoupling capacitors connected in a triangle; the first and second capacitors are formed between the second electrode (311) and the first and the second conducting elements, respectively; the third capacitor is formed between the first and the second elements (313-1) and (313-2). In the case of the conducting elements with a surface of size 1.55 micrometer by 2.8 micrometer, and the insulating layer of thickness 9 micrometer, the three capacitances are: 145 pF, 166 pF, and 166 pF.

公开(公告)号：FR2819091B1

公开(公告)日：2003-04-11

申请号：FR0017294

申请日：2000-12-29

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  JACQUET FRANCOIS

IPC: G11C11/406 ,  G11C11/401 ,  G11C11/402

Abstract: A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

公开(公告)号：FR2830365A1

公开(公告)日：2003-04-04

申请号：FR0112519

申请日：2001-09-28

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  MAZOYER PASCALE ,  FAZAN PIERRE

IPC: G11C7/06 ,  G11C7/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C11/40

Abstract: A DRAM formed of an array of cells, each of which includes a capacitive memory point and a control transistor. The array is formed of the repetition of an elementary pattern extending over three rows and three columns and including six cells arranged so that each of the three rows and each of the three columns of the elementary pattern includes two cells, wherein each column of the elementary pattern includes a first and a second bit line, each first and second bit line being connected to one half of the memory cells included by the column.

公开(公告)号：FR2818425B1

公开(公告)日：2003-04-04

申请号：FR0016399

申请日：2000-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/409 ,  G11C11/40

Abstract: The invention concerns an amplifier ( 1 ), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.

公开(公告)号：FR2773635B1

公开(公告)日：2003-01-10

申请号：FR9800372

申请日：1998-01-15

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  BOUCHE MICHEL

IPC: G11C7/06 ,  G11C11/406 ,  G11C11/407 ,  G11C11/403

公开(公告)号：FR2817997A1

公开(公告)日：2002-06-14

申请号：FR0016029

申请日：2000-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD ,  WADSWORTH ROB

IPC: G11C29/38 ,  G11C7/24 ,  G01R31/317

Abstract: Has logic circuit (40') of NON-OR-EXCLUSIVE type with temporary memory elements (10,20). Respective outputs of all columns of logic circuits are connected to a result line (MATCH) pre-loaded to first state. A logic circuit (40) executes an OR-EXCLUSIVE function and NON-OR-EXCLUSIVE function for states contained in temporary memory elements. The respective results of logic combinations are used to maintain or not pre-loaded state on complementary input-output lines of column. Volatile memory circuit having a number of memory cells (3) in a matrix network, and associated with each column of the network is at least a pair of temporary memory elements (10,20) independently controlled, one from the other. Associated with each pair of temporary memory elements is a logic circuit (40,40') dedicated to memory circuit testing and combing the respective states of the temporary memory elements. The logic circuits are activated by a control signal (TEST') for switching to test mode. Independent Claims are included for - the test method.

公开(公告)号：FR2817996A1

公开(公告)日：2002-06-14

申请号：FR0016033

申请日：2000-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： FERRANT RICHARD

IPC: G11C15/00 ,  G11C15/04 ,  G11C5/02 ,  G06F12/08

Abstract: For each matrix column a second temporary storage flip-flop (34) for complementary signals is read by the amplifier (SAi). The respective functions of the two flip-flops (33,34) are interchangeable. For each matrix column, a unique mask register (37) is designed to inhibit the comparison of the correspondence column . Integrated circuit cache memory which includes a matrix array (10) of memory elements (20) associated, in columns, with two lines of complementary bits (BLi,BLi). Each memory element includes, in series between a first bit line (BLi) and a reference potential, a transistor (T) and capacitor (C). the transistor grid is connected to a word line (WLj); and for each matrix network column; a read amplifier (S Ai) between the bit lines and two complementary read points; a first temporary storage flip-flop (33) for a value to compare with one of the column memory elements, and; a unique element (31) for comparing the contents of the first flip-flop with a state function for one of the read points.