公开(公告)号：FR2886761B1

公开(公告)日：2008-05-02

申请号：FR0505700

申请日：2005-06-06

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

IPC: H01L21/8238

Abstract: Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

公开(公告)号：FR2893181B1

公开(公告)日：2008-01-11

申请号：FR0511424

申请日：2005-11-09

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： BARBE JEAN CHARLES ,  CLAVELIER LAURENT ,  VIANAY BENOIT ,  MORAND YVES

IPC: H01L21/30 ,  H01L21/8238

Abstract: Two active zones are produced on a front face of a support, by forming first active zones (1a-c) with sidewalls covered by a thin protective layer, on a front face (5a) of an insulating thin layer (3); patterning the protective layer (9) to free interface regions in the sidewalls (8a-c) of the active zones; intercalating patterns made of second semi-conducting material in polycrystalline and/or amorphous form; depositing a passivation layer on the first zone and patterns; and crystallizing the second material in monocrystalline form. Production of two active zones on a front face of a support, involves: (A) formation, on the front face of electrically insulating thin layer, of the first active zones with at least side walls covered by a thin protective layer; (B) patterning of the protective layer to free interface regions in the side walls of first active zones; (C) intercalation between the first active zones, on the front face of the insulating thin layer, of patterns made of second semi-conducting material in polycrystalline and/or amorphous form; (D) deposition of a passivation layer on the first active zones and the patterns; and (E) crystallization of the second semi-conducting material in monocrystalline form to form the second active zones. Each pattern comprises at least a part of a side wall in direct contact with an interface region of an adjacent first active zone and a front face disposed in the same plane as the front faces of the first active zones. The zones are formed by two monocrystalline semi-conducting materials that are distinct from one another and comprising coplanar front faces. The support is formed by stacking of a substrate (4) and of an electrically insulating thin layer. A front face of the insulating thin layer constitutes the front face of the support. The first material is germanium or a silicon and germanium alloy. The zones are made of silicon or germanium. An independent claim is included for use of the above method for fabrication of complementary metal oxide semiconductor structures.

公开(公告)号：FR2902234A1

公开(公告)日：2007-12-14

申请号：FR0652094

申请日：2006-06-12

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： DAMLENCOURT JEAN FRANCOIS ,  MORAND YVES ,  CLAVELIER LAURENT

IPC: H01L21/205 ,  H01L21/762

Abstract: L'invention concerne un procédé de réalisation d'un dispositif microélectronique comportant une pluralité de zones semi-conductrices à base de Si1-yGey (avec 0

公开(公告)号：FR2886763B1

公开(公告)日：2007-08-03

申请号：FR0505701

申请日：2005-06-06

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

Inventor： MORAND YVES ,  POIROUX THIERRY ,  VINET MAUD

Abstract: The method involves forming a stack by laminating an inner germanium silicon layer (3) between outer germanium silicon layers (2), in which the germanium concentration of the inner and outer germanium silicon layers are between 10 to 50 percent and between 0 to 10 percent, respectively. A silica layer (6) is formed on the surface of a main zone (5) by performing delineation and lateral thermal oxidation in the stack. Delineation process includes performing anisotropic plasma etching in the stack after deposition and photolithography of a photoresist. An independent claim is also included for: a germanium-based microelectronic component.

公开(公告)号：FR2853452A1

公开(公告)日：2004-10-08

申请号：FR0304008

申请日：2003-04-01

Applicant: ST MICROELECTRONICS SA

Inventor： COSNIER VINCENT ,  MORAND YVES ,  KERMARREC OLIVIER ,  BENSAHEL DANIEL ,  CAMPIDELLI YVES

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51

Abstract: The fabrication of a semiconductor device having a dielectric grid of a material with a high dielectric permittivity includes a stage (40) of deposition, directly on the grid dielectric, of a first layer of Si1-xGex with 0.5 less than x = 1, at a temperature essentially low with respect to the temperature of deposition of poly-Si by thermal chemical vapour deposition. An independent claim is also claimed for the semiconductor device thus fabricated.