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    2.
    发明专利
    未知

    公开(公告)号：DE60302134D1

    公开(公告)日：2005-12-08

    申请号：DE60302134

    申请日：2003-12-22

    Applicant: ST MICROELECTRONICS SA

    Inventor： HALIMAOUI AOMAR ,  BENSAHEL DANIEL

    IPC: H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/51 ,  H01L21/02

    Abstract: A localized region of material difficult to engrave (35) is formed in an IC by: forming a first layer (31) of silicon oxide of less than 1 nm thickness on a substrate (30); depositing a second selectively engravable layer (32); forming an opening (33); selectively growing Ge layer (34); depositing the material difficult to engrave; depositing a conducting layer to fill the opening in the Ge; smoothing to uncover the Ge; and eliminating the Ge and the first and second layers. The opening (33) is formed according to the motif of the localized region in the second layer. The Ge Layer (34) is grown around the opening in the second layer (32). The material which does not easily engrave will not deposit itself on the Ge.

    3.
    发明专利
    未知

    公开(公告)号：FR2853452B1

    公开(公告)日：2005-08-19

    申请号：FR0304008

    申请日：2003-04-01

    Applicant: ST MICROELECTRONICS SA

    Inventor： COSNIER VINCENT ,  MORAND YVES ,  KERMARREC OLIVIER ,  BENSAHEL DANIEL ,  CAMPIDELLI YVES

    IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51

    Abstract: The fabrication of a semiconductor device having a dielectric grid of a material with a high dielectric permittivity includes a stage (40) of deposition, directly on the grid dielectric, of a first layer of Si1-xGex with 0.5 less than x = 1, at a temperature essentially low with respect to the temperature of deposition of poly-Si by thermal chemical vapour deposition. An independent claim is also claimed for the semiconductor device thus fabricated.

    4.
    发明专利
    未知

    公开(公告)号：FR2838237B1

    公开(公告)日：2005-02-25

    申请号：FR0204165

    申请日：2002-04-03

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  BENSAHEL DANIEL

    IPC: H01L21/336 ,  H01L29/06 ,  H01L29/786 ,  H01L27/105

    Abstract: The transistor (T) is situated above a base layer (1) formed on a semiconductor substrate (SB) of a relaxed silicon-germanium alloy, and comprises under the insulated gate (7) a first constrained silicon layer (2) rested on the base layer (1), a buried insulator layer (10) and a second constrained silicon layer (4) extending between the regions of the source (S) and the drain (D) of the transistor. The thickness of the two constrained silicon layers (2,4) and that of the intermediate insulator layer (10) is much less than that of the base layer, and it is a few tens of nanometres, for example 20 nm. The thickness of the base layer (1) is of the order of a few micrometres, for example 2 micrometres. The manufacturing method comprises the formation of the base layer (1) on the silicon substrate (SB), the first constrained silicon layer (2), an intermediate layer of silicon-germanium, the second constrained silicon layer (4), the insulated gate (7) of the transistor flanked by insulating regions (8), an etching of the intermediate layer so to form a tunnel below the insulated gate, filling the tunnel with an insulator material (10), and the formation of the regions of the source (S) and the drain (D). The two constrained silicon layers (2,4) and the intermediate layer are formed by non-selective epitaxy, and an isolation zone (5) is formed in upper part of the base layer compatible with non-relaxation of constraints in the constrained silicon layers.

    7.
    发明专利
    未知

    公开(公告)号：FR2857155B1

    公开(公告)日：2005-10-21

    申请号：FR0307982

    申请日：2003-07-01

    Applicant: ST MICROELECTRONICS SA

    Inventor： HALIMAOUI AOMAR ,  BENSAHEL DANIEL

    IPC: H01L21/20 ,  H01L21/324 ,  H01L21/322

    Abstract: Fabrication of a stressed layer of silicon or silicon-germanium alloy comprises: (a) formation of a layer (2) of silicon or silicon-germanium alloy on a layer (1) of a material having a modifiable mesh parameter; and (b) modification of the mesh parameter.

    10.
    发明专利
    未知

    公开(公告)号：FR2842217A1

    公开(公告)日：2004-01-16

    申请号：FR0208862

    申请日：2002-07-12

    Applicant: ST MICROELECTRONICS SA

    Inventor： BENSAHEL DANIEL

    IPC: C30B25/02 ,  C30B25/18 ,  H01L21/20 ,  H01L29/04 ,  C30B29/40 ,  C30B29/42 ,  C30B29/08 ,  H01L21/8252

    Abstract: The growth of a monocrystalline region (22) of a III-V compound on surface corresponding to a crystallographic plane of a substrate (10) of monocrystalline silicon consists of: (a) the epitaxial growth of a layer (12) of monocrystalline germanium on the substrate; (b) engraving, in a part of the thickness of this germanium layer, an opening (14) of which the bottom corresponds to a single face or to several faces (18, 20) inclined with respect to the surface; (c) growing the monocrystalline III-V compound on the bottom of the opening. An Independent claim is also included for a device comprising a monocrystalline silicon substrate incorporating a surface corresponding to a crystallographic plane coated with a layer of germanium and a III-V compound.

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