公开(公告)号：FR2801420A1

公开(公告)日：2001-05-25

申请号：FR9914746

申请日：1999-11-23

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L29/732

Abstract: Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector on a layer of extrinsic collector in a semiconductor substrate; (b) making a lateral isolating region; (c) making a base next to he intrinsic collector and the lateral isolating region; and (d) making a bipartite dope emitter in situ. Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector (4) on a layer of extrinsic collector (2) in a semiconductor substrate (1); (b) making a lateral isolating region (5) surrounding the upper part of the intrinsic collector and of wells of the imprisoned extrinsic collector (60); (c) making a base (8) next to he intrinsic collector and the lateral isolating region and comprising a non-selective epitaxy of a semiconductor region (8) comprising at least one layer of silicon; (d) making a bipartite dope emitter (11) in situ comprising: (i) making a first layer (110) of the emitter formed from microcrystalline silicon and directly in contact with a part (800) of the upper surface of the semiconductor region situated on top of the intrinsic collector; and (ii) making a second part (111) of emitter from polycrystalline silicon; the two parts (110, 111) being separated by an oxide layer (112).

公开(公告)号：FR3027156A1

公开(公告)日：2016-04-15

申请号：FR1459727

申请日：2014-10-10

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  ST MICROELECTRONICS SA

Inventor： FAVENNEC LAURENT ,  DUTARTRE DIDIER ,  ROY FRANCOIS

IPC: H01L31/0248 ,  H01L27/146

Abstract: L'invention concerne un procédé de fabrication d'une photodiode pincée, comprenant : la formation d'une région (13) de conversion de photons en charges électriques d'un premier type de conductivité sur un substrat (11, 12) du deuxième type de conductivité ; le revêtement de ladite région par une couche d'un isolant (22) fortement dopé du deuxième type de conductivité ; et un recuit assurant une diffusion de dopants en provenance de la couche d'isolant fortement dopé.

公开(公告)号：FR2890662B1

公开(公告)日：2008-09-19

申请号：FR0509397

申请日：2005-09-14

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  LOUBET NICOLAS ,  TALBOT ALEXANDRE

IPC: C30B25/02 ,  H01L21/205 ,  H01L21/762

Abstract: The low temperature epitaxy process on a surface of plate containing pure silicon material/silicon alloy in rapid thermal chemical vapor deposition equipment to reduce creeping by diffusion of surface of the plate, comprises charging the plate in an equipment at 400-500[deg]C, and preparing a surface to deposit new chemical species. The deposition is carried out at low epitaxial temperature of less than 750[deg]C. Temperature in the chemical deposition equipment increases the charging temperature of the plate up to depositing temperature without extending. The low temperature epitaxy process on a surface of plate containing pure silicon material/silicon alloy in rapid thermal chemical vapor deposition equipment to reduce creeping by diffusion of surface of the plate, comprises charging the plate in an equipment at 400-500[deg]C, and preparing a surface to deposit new chemical species. The deposition is carried out at low epitaxial temperature of less than 750[deg]C. Temperature in the chemical deposition equipment increases the charging temperature of the plate up to depositing temperature without extending. The preparation of plate surface comprises a permanent passivation surface, which is carried out by injecting gas/mixture of active gases at 400-500[deg]C, pre cleaning surface of the plate, and eliminating oxides by a treatment with hydrofluoric acid. The gas/mixture of active gases comprises a gas containing hydrochloric acid, and silane or dichlorosilane. Desorption takes place during increase in the temperature. The gas/mixture of active gases are introduced by surface passivation is different from the gas/mixture of gases are injected for deposition. The dichlorosilane acts as active gas and silane as deposition gas. Precursor of active gas is silicon and the precursor of deposition gas is silicon and germanium. The gas/mixture active gases for passivation have slower depository kinetics than the kinetics of gas/mixture of gases for the deposition. The mixture of active gases is adjusted by an adjustor to obtain depository kinetics, which is almost zero. The injection of gas/mixture of active gases is carried out after charging the plate.

公开(公告)号：FR2900277B1

公开(公告)日：2008-07-11

申请号：FR0603453

申请日：2006-04-19

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  RUBALDO LAURENT ,  TALBOT ALEXANDRE

IPC: H01L21/306

Abstract: The method involves heating a silicon on isolator-MOS (SOI-MOS) type substrate (100) and forming a silicon base layer (1) on a surface (S) of the substrate, in adapted conditions such that the layer is monocrystalline in reduced zones (101) of the substrate and amorphous in insulating parts (102) of the substrate, by placing a gas mixture having molecules of non-chlorinated silane and carrier gas in contact with the substrate. The formed layer is engraved such that an amorphous portion of the layer is removed, and a monocrystalline portion (2) of the layer remains intact.

公开(公告)号：FR2890662A1

公开(公告)日：2007-03-16

申请号：FR0509397

申请日：2005-09-14

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  LOUBET NICOLAS ,  TALBOT ALEXANDRE

IPC: H01L21/205 ,  C30B25/02 ,  H01L21/762

Abstract: Procédé d'épitaxie à faible budget thermique et son utilisation.L'invention concerne un procédé d'épitaxie basse température à la surface d'au moins une plaque en matériau à base de silicium pur ou d'alliage de silicium (SiGe, SiC, SiGeC...), dans un équipement de dépôt chimique en phase vapeur (CVD), notamment à thermique rapide (RTCVD), le procédé comprenant au moins les étapes consistant à :- charger la plaque dans l'équipement, à une température de chargement,- préparer la surface en vue d'un dépôt de nouvelles espèces chimiques,- effectuer, postérieurement à la préparation de la surface, le dépôt dans des conditions d'épitaxie basse température ( > >procédé dans lequel la préparation de la surface comprend une étape de passivation de la surface par injection de gaz-ou de mélange de gaz- actif.

公开(公告)号：DE60214463D1

公开(公告)日：2006-10-19

申请号：DE60214463

申请日：2002-04-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  RIBOT PASCAL

IPC: H03H9/24 ,  H03H3/00

Abstract: A resonator formed by the steps of defining an active single-crystal silicon layer delimited by a buried insulator layer, depositing a silicon-germanium layer by a selective epitaxy method so that the silicon-germanium layer grows above the active single-crystal silicon area, depositing by a non-selective epitaxy method a silicon layer and etching it according to a desired contour, and removing the silicon-germanium by a selective etching with respect to the silicon and to the insulator.

公开(公告)号：FR2823032B1

公开(公告)日：2003-07-11

申请号：FR0104510

申请日：2001-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  RIBOT PASCAL

IPC: H03H3/00 ,  H03H9/24 ,  H03H9/00

Abstract: A resonator formed by the steps of defining an active single-crystal silicon layer delimited by a buried insulator layer, depositing a silicon-germanium layer by a selective epitaxy method so that the silicon-germanium layer grows above the active single-crystal silicon area, depositing by a non-selective epitaxy method a silicon layer and etching it according to a desired contour, and removing the silicon-germanium by a selective etching with respect to the silicon and to the insulator.

公开(公告)号：FR2813707B1

公开(公告)日：2002-11-29

申请号：FR0011419

申请日：2000-09-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

公开(公告)号：FR2801420B1

公开(公告)日：2002-04-12

申请号：FR9914746

申请日：1999-11-23

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L29/732

Abstract: Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector on a layer of extrinsic collector in a semiconductor substrate; (b) making a lateral isolating region; (c) making a base next to he intrinsic collector and the lateral isolating region; and (d) making a bipartite dope emitter in situ. Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector (4) on a layer of extrinsic collector (2) in a semiconductor substrate (1); (b) making a lateral isolating region (5) surrounding the upper part of the intrinsic collector and of wells of the imprisoned extrinsic collector (60); (c) making a base (8) next to he intrinsic collector and the lateral isolating region and comprising a non-selective epitaxy of a semiconductor region (8) comprising at least one layer of silicon; (d) making a bipartite dope emitter (11) in situ comprising: (i) making a first layer (110) of the emitter formed from microcrystalline silicon and directly in contact with a part (800) of the upper surface of the semiconductor region situated on top of the intrinsic collector; and (ii) making a second part (111) of emitter from polycrystalline silicon; the two parts (110, 111) being separated by an oxide layer (112).

公开(公告)号：FR2812764A1

公开(公告)日：2002-02-08

申请号：FR0010176

申请日：2000-08-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  HAOND MICHEL ,  DUTARTRE DIDIER

IPC: H01L21/762 ,  H01L21/328

Abstract: Substrate production involves epitaxially growing semiconductor layers on an initial substrate (1), defining and masking active zones, forming spacers and trenches, lateral etching of the first epitaxial layer, filling the formed tunnel with a dielectric for a Silicon-On-Insulator (SOI) substrate or leaving void for a Silicon-On-Nothing (SON) substrate, and filling the trenches with a dielectric. Production of a SOI substrate involves: (a) epitaxial growth, in sequence, of a Ge or SiGe layer and a Si layer (3) on an initial, preferably Si, substrate; (b) defining and masking active zones; (c) forming insulating spacers (7) in trench zones around the perimeter of each active zone at predetermined intervals and back-to-back with the sides of the active zones; (d) etching the trenches; (e) lateral etching of the Ge or SiGe layer; (f) filling the formed laterally etched space (tunnel) (8) with a dielectric, preferably SiO2, or passivation of tunnel walls followed by filling the tunnel (8) with a dielectric different from SiO2; (g) filling the trenches with a dielectric, preferably SiO2; and (h) performing finishing operations. Production of a SON substrate involves the same procedure except that stage (f) is omitted and passivation of the tunnel walls can be carried out prior to filling the trenches with a dielectric. The thickness of the Ge or SiGe layer is 1-50 nm, preferably 10-30 nm, and the thickness of the Si layer (3) is 10-50 nm, preferably 5-20 nm. Following the finishing operations a 'bulk' zone is produced in the SOI or SON substrate by masking, using a resin, the region that must be retained, followed by removal of layers in the unmasked region. A multilayer of alternating Si layers (3) and Ge or SiGe layers (2) can be formed in stage (a) of the SOI or SON substrate production process. Independent claims are given for: (i) a substrate having at least one active SOI active zone surrounded by isolating trenches; and (ii) a substrate having at least one active SOI active zone surrounded by isolating trenches.