公开(公告)号：DE69515991D1

公开(公告)日：2000-05-04

申请号：DE69515991

申请日：1995-05-19

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C11/417 ,  G11C7/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0948 ,  G11C7/00 ,  G11C11/409

Abstract: An output stage for integrated circuits, particularly for electronic memories, comprising: an input section that is adapted to acquire an input datum; a latch circuit having a first output and a second output and connected to the input section; a first inverter connected to the second output; a second inverter connected to the first output; a third inverter connected to the output of the second inverter; a grounding transistor driven by the second output of the latch circuit and adapted to connect the output of the third inverter to the ground; and a push-pull stage driven by the output of the first and third inverters. The stage according to the present invention furthermore comprises: a shorting transistor adapted to connect the output of the first inverter to the output of the second inverter; a first enabling transistor interposed between the first inverter and the first output of the latch circuit; a second enabling transistor interposed between the second inverter and the second output of the latch circuit; and a section for charging and discharging the push-pull stage, which is adapted to rapidly discharge the gate of the first transistor of the push-pull stage and to charge the gate of the second transistor of the push-pull stage during their operation.

公开(公告)号：DE69319886D1

公开(公告)日：1998-08-27

申请号：DE69319886

申请日：1993-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： OLIVO MARCO ,  PASCUCCI LUIGI

IPC: G11C11/00 ,  G11C29/04 ,  G11C29/00

Abstract: There is described a semiconductor memory comprising a matrix of lines and columns of memory cells, wherein the columns (BL) are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets (1) of columns, and there are redundancy columns (BLR) suitable for replacing a matrix column (BL) containing defective memory cells. Each of the redundancy columns (BLR) is included in a respective packet (1). The memory also comprises control circuits (5,6,7) to execute the abovementioned replacement.

公开(公告)号：IT1253680B

公开(公告)日：1995-08-22

申请号：ITVA910027

申请日：1991-08-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C17/18 ,  G11C8/10 ,  G11C17/12 ,  G11C

Abstract: A decoder for a ROM matrix organized in selectable NAND parcels of cells utilizes four selection means driven through five buses for implementing a two-level decoding, thus driving a fractionary number of rows through a plurality of selectable drivers. The architecture of the row decoder, based on a subdivision into a plurality of row drivers renders the circuitry physically compatible with the geometrical constraints imposed by a particularly small pitch of the cells. Subdivision of row drivers has positive effects also on access time, reliability and overall performance of the memory as compared to a memory provided with a decoder of the prior art driving in parallel all the homonymous rows of all the selectable NAND parcels of cells.

公开(公告)号：DE60041954D1

公开(公告)日：2009-05-20

申请号：DE60041954

申请日：2000-02-14

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C8/04 ,  G11C7/10 ,  H03K23/66

Abstract: A memory counter circuit, comprising a plurality of mutually connected counter stages (1a, 1), comprising: an internal address bus (2) which is interfaced with each one of the counter stages (1a, 1) and is adapted to send an external address signal (18) to each one of the counter stages; means (19, 20) for loading the external address signal (18) onto the internal address bus (2); means (3) for enabling the connection between the internal bus (2) and each one of the counter stages (1a, 1), the means being driven by a true address latch enable signal (ALE); means (15) for generating the true address latch enable signal (ALE) starting from an external address latch signal (16) and a fast address latch enable signal (ALE-fast) which is adapted to drive the means (19, 20) for loading the external address (18) onto the internal address bus (2); and means (21) for generating clock signals (M-inc, S-inc) for synchronizing each one of the counter stages (1a, 1), the synchronization signals not being simultaneously active.

公开(公告)号：DE60041263D1

公开(公告)日：2009-02-12

申请号：DE60041263

申请日：2000-10-18

Applicant: ST MICROELECTRONICS SRL

Inventor： TOMAIUOLO FRANCESCO ,  NICOSIA SALVATORE ,  PASCUCCI LUIGI

IPC: G11C7/10 ,  G11C8/00

Abstract: A new multipurpose interlaced memory device functions in two different modes: synchronous and asynchronous, using a circuit for detecting address transitions that by acting as a synchronous clock of the system lets the control circuit of the memory device recognize the required access mode by enabling a comparison of the currently input external address with the one stored in the address counters of the two banks of cells. The memory device has a buffer for outputting a datum provided with means that for pre-charging the output nodes to an intermediate voltage between the voltages corresponding to the two possible logic states, thus reducing noise and improving transfer time.

公开(公告)号：DE60212938D1

公开(公告)日：2006-08-17

申请号：DE60212938

申请日：2002-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34

公开(公告)号：DE69634294D1

公开(公告)日：2005-03-10

申请号：DE69634294

申请日：1996-04-05

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G11C14/00

Abstract: The present invention concerns an auto-saving circuit (1) for programming configuration elements of non-volatile memory cells organized in a cells matrix in a memory device integrated on a semiconductor with said circuit being inserted between a first (Vdd) and a second (GND) power supply reference voltage and being powered also by programming voltages (Vpcx,Vpcy) generated inside the memory device to produce at output programming signals (UPR-CG,UPR-PG) of the configuration elements. The circuit in question comprises a first (2) and a second (3) circuit portion, one for each signal output (U1,U2) and each powered by a respective programming voltage (Vpcx,Vpcy) and each comprising a switching network with at least one high threshold transistor (P2,P9) and decoupling elements (Ca,Cb,Ck,Cp) to give inertia to the circuit against electrostatic discharges or accidental power supply variations.

公开(公告)号：DE69633912D1

公开(公告)日：2004-12-30

申请号：DE69633912

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI

IPC: G05F3/26 ,  G11C16/30 ,  G11C16/06

Abstract: A circuit for the generation of a voltage as a function of the conductivity of an elementary cell, particularly for non-volatile memories, comprising a non-volatile element (1) that is substantially identical to a generic cell of a memory matrix; a structure (2) for biasing the drain terminal of the non-volatile element (1); a branch for sensing the current that flows through the non-volatile element; and a branch for mirroring the current sensed by the current sensing branch, the mirroring branch containing at least one transistor (8) the gate terminal whereof is controlled by a first output voltage (V=f(Icell)). The mirroring branch produces the first output voltage, the value whereof is a function of the current (Icell) that flows through the non-volatile element and is sensed by the current sensing branch, and the biasing structure (2) produces a second voltage that is substantially constant (Vref) and is used as a reference voltage for the first voltage (V=f(Icell)).

公开(公告)号：DE69633774D1

公开(公告)日：2004-12-09

申请号：DE69633774

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  FONTANA MARCO ,  BARCELLA ANTONIO

IPC: G11C16/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/00

Abstract: A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, characterized in that the memory is divided into at least two memory half-matrices that are arranged on different half-planes, and in that the circuit comprises, for each one of the at least two memory half-matrices, a reference unit (3i) for each one of the at least two memory half-matrices and an associated unit (4) for reproducing the propagation of the signals along the reference unit, the reference unit (3i) and the associated propagation reproduction unit (4) having a structure that is identical to each generic word line of the memory device, the reference and propagation reproduction units of one of the at least two memory half-matrices being activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit (4), the conditions for starting correct and certain reading of the selected memory cell.

公开(公告)号：DE69631284D1

公开(公告)日：2004-02-12

申请号：DE69631284

申请日：1996-03-29

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  FONTANA MARCO

IPC: G11C5/02 ,  G11C16/28 ,  G11C16/06