公开(公告)号：EP1858157B1

公开(公告)日：2009-07-01

申请号：EP07108245.7

申请日：2007-05-15

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Chawla, Nitin

IPC: H03C3/09 ,  H04B1/69 ,  H03B29/00 ,  H03L7/197

CPC classification number: H04B1/69 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/1976 ,  H03M7/3026 ,  H03M7/3042

公开(公告)号：EP1742364A3

公开(公告)日：2008-12-31

申请号：EP06116225.1

申请日：2006-06-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kumar, Niraj ,  Agrawal, Vinayak ,  Garg, Paras

IPC: H03K19/0185

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: An improved input buffer for CMOS integrated circuits using sub-micron CMOS technology is described. The devices in sub-micron CMOS technology are affected by the presence of high voltage between various ports of a device. An input voltage limiting circuit is provided, resulting in high voltage tolerant input buffer with low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to the manufacturing process variations by adding compensation devices to the first inverter stage in the input buffering stage and thus increases the noise margin. The hysteresis characteristic produced by the circuit has reduced effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding any possibility of DC current flow in the circuitry.

公开(公告)号：EP1976226A1

公开(公告)日：2008-10-01

申请号：EP08153587.4

申请日：2008-03-28

Applicant: STMicroelectronics Pvt. Ltd. ,  STMicroelectronics Belgium N.V.

Inventor： Gupta, Naresh Kumar ,  Maheshwari, Rajat ,  Charlier, Vincent ,  Vermeire, Gerrit

IPC: H04L29/06

CPC classification number: H04L69/32 ,  H04L69/12 ,  H04W52/0258 ,  H04W76/10 ,  Y02D70/144

Abstract: The present invention discloses a system and a methodology for enhancing performance during wireless communications by reducing system latency, MIPS requirements and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller retrieves certain information required for data transmission and stores the same locally, the data source provides data directly to the controller without routing the data through the host. The host is relieved of the data processing that needs to be done while the data is being transferred. Hence, the overall latency of the system is improved because of the optimal routing of data traffic. The host can even go to lower power modes while the controller is performing the data operations on behalf of the upper layer stack thereby saving power consumption of the overall system.

Abstract translation: 本发明盘松系统以及用于通过减少系统等待时间，MIPS需求和功率消耗提高在无线通信期间的性能的方法。 本发明盘松动的系统和在上层堆栈处理的哪一部分的无线数据通信的方法中执行的控制器上，以减轻someData密集型操作的主处理器。 初始连接建立阶段，其中控制器在本地检索数据传输所需的某些信息，并存储相同的后，数据源直接提供数据到控制器，而不通过主机路由该数据。 主机被解除了数据处理的根本需求，而数据被传输到完成。 因此，系统的总体等待时间由于数据通信的最优路由，改进。 主机甚至可以到低功率模式的同时，所述控制器被代表上层堆栈从而节省了整个系统的功耗的执行数据操作。

公开(公告)号：EP1898630A2

公开(公告)日：2008-03-12

申请号：EP07114687.2

申请日：2007-08-21

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Mohan Sharma, Vivek ,  Kumar Jain, Sheetal

IPC: H04N5/00

CPC classification number: H04N21/2368 ,  H04N5/40 ,  H04N21/2383

Abstract: The present invention provides a digital radio frequency (RF) modulator for providing modulation for base-band TV signals. The RF modulator provides direct conversion of digital base-band audio and video signals to a desired RF channel frequency, without any analogue up conversion. The RF modulator in the present invention includes an audio module, a video module, and a RF converter. The audio module includes a pre-emphasis filter, a multi-stage audio interpolator and a complex frequency modulator to generate frequency modulated (FM) audio signals. The video module includes a complex VSB filter, a group-delay compensation filter and some processing logic to generate a filtered output video signal. The RF converter includes a complex adder, a complex multiplier and a RF interpolator to construct the base band TV signals and to shift the base band TV signals in a frequency domain to the desired RF channel frequency. The exponential video carrier is generated at baseband and has a frequency whose value is in the range of +/-13.5MHz. The RF interpolator includes a zero pad logic followed by a quadrature band pass filter (BPF), and an optional second stage of another zero-pad logic followed by a real band pass filter (BPF). The second stage is optional in the sense that it is required only if the desired RF channel is in the higher VHF band.

Abstract translation: 本发明提供一种用于提供基带电视信号调制的数字射频（RF）调制器。 RF调制器可将数字基带音频和视频信号直接转换为所需的RF信道频率，无需任何模拟上转换。 本发明的RF调制器包括音频模块，视频模块和RF转换器。 音频模块包括预加重滤波器，多级音频内插器和复频调制器以产生调频（FM）音频信号。 视频模块包括复合VSB滤波器，组延迟补偿滤波器和用于产生经滤波的输出视频信号的一些处理逻辑。 RF转换器包括复数加法器，复数乘法器和RF内插器，以构建基带TV信号并将频域中的基带TV信号移位到期望的RF信道频率。 指数视频载波在基带处产生，其频率范围为+/- 13.5MHz。 RF内插器包括跟随正交带通滤波器（BPF）的零焊盘逻辑，以及随后是实数带通滤波器（BPF）的另一零焊盘逻辑的可选的第二级。 在第二阶段是可选的，只有当所需的RF信道处于较高VHF频带时才需要。

公开(公告)号：EP1662660A3

公开(公告)日：2007-12-12

申请号：EP05025953.0

申请日：2005-11-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Sushil Kumar ,  Garg, Paras

IPC: H03K19/003 ,  H03K3/011 ,  H03K17/14

CPC classification number: H03K3/011 ,  H03K3/3565 ,  H03K17/145 ,  H03K19/00384

Abstract: In the present invention an apparatus and method for providing compensation against temperature, process and supply voltage variation in MOS circuits has been proposed. The invention provides a change in process, temperature and voltage detection circuit, which controls the body bias and the drive of the devices in the CMOS circuit. The detection circuit is independent of any input or internal signal of the CMOS circuit to be controlled.

公开(公告)号：EP1858157A1

公开(公告)日：2007-11-21

申请号：EP07108245.7

申请日：2007-05-15

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Chawla, Nitin

IPC: H03C3/09 ,  H04B1/69 ,  H03B29/00 ,  H03L7/197

CPC classification number: H04B1/69 ,  H03C3/0925 ,  H03C3/0933 ,  H03L7/1976 ,  H03M7/3026 ,  H03M7/3042

Abstract: The present invention provides a spread spectrum clock generation system, comprising a digitally controlled Phase Locked Loop (PLL), and a Digital Frequency Profile Generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with a multilevel error feedback noise shaping structure that provides the required Noise Transfer Function for the quantization noise but maintains a unity gain all pass signal transfer function. This arrangement offers minimal degradation of the in-band Signal-to-Noise-Ratio (SNR) at the cost of higher out-of-band noise.

Abstract translation: 本发明提供一种包括数字控制的锁相环（PLL）和数字频率分布生成器的扩展频谱时钟生成系统，用于为了实现输出频率调制时钟中的频谱平坦度而创建近似最佳频率调制曲线。 该电路与多电平误差反馈噪声整形结构相结合，为结构量化噪声提供所需的噪声传递函数，但保持单位增益全通信号传递功能。 这种布置以较高的带外噪声为代价，可以降低带内信噪比（SNR）。

公开(公告)号：EP1667009B1

公开(公告)日：2007-11-14

申请号：EP05111629.1

申请日：2005-12-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Jaisinghani, Pooja ,  Nandy, Tapas

IPC: G06F1/28 ,  G06F1/26 ,  G01R19/165 ,  G11C16/30

CPC classification number: G01R19/16576 ,  G01R19/16538 ,  Y10T307/735 ,  Y10T307/74

公开(公告)号：EP1630958A3

公开(公告)日：2007-03-07

申请号：EP05018679.0

申请日：2005-08-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bhuvanagiri, Aditha ,  Singh, Halvinder ,  Malik, Rakesh ,  Chawla, Nitin

IPC: H03H17/06 ,  H03H17/02

CPC classification number: H03H17/0275 ,  H03H17/0657

Abstract: A minimal area integrated circuit implementation of a polyphase interpolation filter using symmetry of coefficients for at least one channel of input data, comprising, an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a channel select multiplexer block selecting a channel in response to a first set of internal control signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals , an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block for synchronization of filtered signal, and a control block to generate clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware requirement of coefficient set implementation in a polyphase interpolation filter.

公开(公告)号：EP1742364A2

公开(公告)日：2007-01-10

申请号：EP06116225.1

申请日：2006-06-28

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kumar, Niraj ,  Agrawal, Vinayak ,  Garg, Paras

IPC: H03K19/0185

CPC classification number: H03K19/00384 ,  H03K19/018521

Abstract: An improved input buffer for CMOS integrated circuits using sub-micron CMOS technology is described. The devices in sub-micron CMOS technology are affected by the presence of high voltage between various ports of a device. An input voltage limiting circuit is provided, resulting in high voltage tolerant input buffer with low voltage tolerant CMOS devices. This improvement also reduces the switching level uncertainty due to the manufacturing process variations by adding compensation devices to the first inverter stage in the input buffering stage and thus increases the noise margin. The hysteresis characteristic produced by the circuit has reduced effect of manufacturing process variation. The circuit can be easily interfaced to other blocks and safely operates in conjunction with relatively high voltage CMOS technology circuitry while achieving the high-speed advantage of thin gate oxide. Low power consumption is achieved by avoiding any possibility of DC current flow in the circuitry.

Abstract translation: 描述了使用亚微米CMOS技术的CMOS集成电路的改进的输入缓冲器。 亚微米CMOS技术中的器件受器件各个端口之间存在高电压的影响。 提供了一个输入电压限制电路，从而产生具有低电压容限CMOS器件的高耐压输入缓冲器。 这种改进还通过在输入缓冲级中将补偿装置添加到第一反相器级而由于制造工艺变化而降低开关级不确定性，并因此增加噪声容限。 由电路产生的滞后特性降低了制造工艺变化的影响。 该电路可以容易地连接到其他块并且与较高电压CMOS技术电路一起安全地工作，同时实现薄栅极氧化物的高速优势。 通过避免电路中的直流电流流动的任何可能性来实现低功耗。

公开(公告)号：EP1443650A3

公开(公告)日：2006-11-15

申请号：EP04001539.8

申请日：2004-01-26

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Nautiyal, Vivek ,  Kumar, Ashish

IPC: H03K19/00

CPC classification number: G11C5/063 ,  H03K19/0019

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution, comprising a plurality of signal lines, an intermediate floating virtual source / sink, and a charge redistribution circuit connected to each said signal line that isolates said line from its source and connects it to the intermediate floating virtual source / sink during an idle period prior to a change of state.
This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary line.