公开(公告)号：JPH09134337A

公开(公告)日：1997-05-20

申请号：JP14605596

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： JIYON SHII KURAUSU ,  DEIBUITSUDO JIEI GAASHIA ,  ROBAATO DABURIYUU HOOSUTO ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO POORU SOONIA ,  UIRIAMU JIYOERU WATOSON ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a single system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: The digital information are communicated among plural processing system elements in the form of a message packet which includes the data to identify these system elements as addresses. Then plural port means of an input/output routing device correspond to the processing system elements and transmit and receive in 2-way fashion the message packet to each other. Furthermore, the routing means answers the address identification data, checks the message packet and sends an error mark to the message packet if an error is detected in order to select one of those port means which are connected together so as to enable a processing system element to send the message packet to another.

公开(公告)号：JPH09134332A

公开(公告)日：1997-05-20

申请号：JP14523096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： SUTEIIBUN SHII MEIAAZU ,  JIYON MAIKERU BURAUN ,  UIRIAMU EFU BURUTSUKAATO ,  JIEEMUZU SUTEIIBUNSU KURETSUKA

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system which can attain the fail-first, fail-functional and fault tolerant actions. SOLUTION: This multiprocessor system includes the sub-processor systems 10A and 10B which have the substantially same constitution. The CPU 12A and 12B of systems 10A and 10B can communicate with the I/O devices 171 to 17n or the CPU of the multiprocessor system via the routing devices 14A and 14B. The communication is performed between the I/O devices and the multiplexed CPUs by means of the messages which are turned into a packet. These CPUs and I/O devices are written into or read out of the CPU of the multiprocessor system. The protection of the CPU memory is maintained by every CPU that has a priority check function of the read/write operations which are carried out against the CPU memory.

公开(公告)号：JPH09128353A

公开(公告)日：1997-05-16

申请号：JP14605696

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： DEIBUITSUDO POORU SOONIA ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU PATAASON BANTON ,  JIYON SHII KURAUSU ,  KENISU EICHI POOTAA ,  UIRIAMU JIYOERU WATOSON ,  RINDA ERIN ZARUZAARA

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To reduce the processing system cost by providing an error inspecting function and masking a fault through hardware in duplex mode operation. SOLUTION: A data processing system 10 is equipped with two subprocessor systems 10A and 10B which have the same constitution and functions. This pair of the subprocessor systems 10A and 10B include a processor device (CPU) 12, a router 14, and an I/O packet interface 16 having a relative I/O device 17. Each of the pair of the CPUs 12 receive an error signal and returns an echo-back error signal to a couple of data communication elements. Then it is determined whether or not each CPU 12 continues to operate according to the error signal and echo-back error signal; and then one of the CPUs 12 continues to operate and the other CPU 12 finishes operating.

公开(公告)号：JPH0950418A

公开(公告)日：1997-02-18

申请号：JP14573296

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： MAAKU FUIRITSUPUSU ,  JIYON ESU DEI ROO ,  ANDORIASU II HOOTEI ,  ROBAATO DABURIYUU RETSUDO

IPC: G06F12/00 ,  G06F9/46 ,  G06F9/50 ,  G06F13/00 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To distribute the calculation loads of a customer information control system over a set of loose coupled parallel processors and to provide an API (application program interface) provided with a transaction serialization control function. SOLUTION: A distributed computer system 100 is provided with plural end user terminals 102 and plural loose coupled server computers for not mutually sharing resources and many user application processes 116 are distributed to the server computers. A first server computer is allocated so as to tentatively store the queue of data recording. The respective user application processes 116 respond to the execution of a WriteQ TS instruction and store at least one piece of TS data for indicating specified data in a tentative storage file. Each TS data recording is provided with a primary key for indicating the position of recording in a specified tentative storage queue. The respective user application processes respond to the execution of a ReadQ TS instruction for specifying the tentative storage queue to retrieve the data and read at least one piece of the TS data recording from the tentative storage file.

公开(公告)号：JPH08263356A

公开(公告)日：1996-10-11

申请号：JP888496

申请日：1996-01-23

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU JIEI KAAREI ,  JIEEMUZU EI RAIAN ,  MASHIYUU SHII MATSUKURIIN ,  MAIKERU JIEI SUKAAPEROSU

IPC: G06F12/00 ,  G06F1/00 ,  G06F21/00 ,  G06F21/24

Abstract: PROBLEM TO BE SOLVED: To provide a method for limiting alteration access to a reserve sub volume only to an application process requiring to perform such access. SOLUTION: System critical files are protected so as not to be altered or eliminated by carelessness by placing them in the reserve name space of a storage device and requiring a process requesting the alteration access to the reserve name space to be provided with a right to do so. The right to the alteration access is acquired by the process of calling a system library processing procedure for altering a memory storage data structure relating to the called process first and identifying that the process is provided with the right to perform the alteration access to the reserve name space. A trial for altering, eliminating or preparing the file present in the reserve name space is denied without such a right.

公开(公告)号：JP2541933B2

公开(公告)日：1996-10-09

申请号：JP13104886

申请日：1986-06-05

Applicant: TANDEM COMPUTERS INC

Inventor： RICHAADO DABURYUU KAA

IPC: G06F15/177 ,  G06F11/00 ,  G06F11/18 ,  G06F11/20 ,  G06F15/16 ,  G06F15/173

公开(公告)号：JP2540197B2

公开(公告)日：1996-10-02

申请号：JP28870088

申请日：1988-11-15

Applicant: TANDEM COMPUTERS INC

Inventor： OORANGUZEBU KEI KAAN

IPC: H03K19/0175 ,  H03K19/018 ,  H03K19/082

公开(公告)号：JP2509758B2

公开(公告)日：1996-06-26

申请号：JP50247190

申请日：1990-01-10

Applicant: TANDEM COMPUTERS INC

Inventor： FUAASHOO JOOGU YUU ,  DEIUISU HYUU EMU JUNIA ,  HANTO KURISUTOFUAA AREN

IPC: H01R13/629 ,  H01R13/639

公开(公告)号：JPH0855076A

公开(公告)日：1996-02-27

申请号：JP15256595

申请日：1995-05-25

Applicant: TANDEM COMPUTERS INC

Inventor： TOOMASU DABURIYU SABEEJI

IPC: G06F13/14 ,  G06F12/06

Abstract: PURPOSE: To comparatively easily establish address sequence required in specified use by continuing a step for generating a bit pattern showing a next address until the last address in sequence is obtained. CONSTITUTION: A plural bits address bus 25 mounting a physical device address is provided for an SCSI bus 10 and the bus 10 is connected to a host device generating plural bit codes called as anchor patterns given to the upper end part 27 of the bus 25. The address bus 25 has plural anchor pattern conversion elements 28 on the intermediate positions of the connection point of the SCSI bus device. The orders of 0-13 are given to fourteen conductors in the address bus 25 and three tap connections extend from the conductor numbers 1, 4 and 10. In the respective conversion elements 28, the conductors of respective fields are connected so that they execute one rank shift of the respective conductors in a designated direction at every field. The last conductor in a shift direction is returned and connected to the first conductor in the field.

公开(公告)号：JPH0844683A

公开(公告)日：1996-02-16

申请号：JP3636995

申请日：1995-02-24

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO

IPC: G06F11/00 ,  G06F15/80 ,  G06F15/16 ,  G06F15/173

Abstract: PURPOSE: To construct a large-scaled parallel processing system with a band width which can be used for access to data held by the system in which each processor unit has high availability. CONSTITUTION: A large-scaled parallel processor is constituted by connecting many individual processor units. Plural processor parts 12 including one or plural processor units mutually connected for data communication by a redundant bus mechanism is formed. Then, the processor parts 12 are mutually connected by a toroidal constitution, and the array of horizontal and vertical rows is formed. Each processor part 12 is connected with the four adjacent processor parts 12 through dual communication paths 14 and 16. Thus, at least two individual paths are provided for data communication from one arbitrary processor unit to another arbitrary processor unit. Each processor unit includes an individual input/output bus mechanism which can be used for mutually connecting the processor part array in extension to three dimension.