公开(公告)号：KR1019950015032A

公开(公告)日：1995-06-16

申请号：KR1019930024330

申请日：1993-11-16

Applicant: 한국전자통신연구원

Inventor： 모상만 ,  원철호 ,  윤석한 ,  윤용호 ,  오길록

IPC: G06F1/06

Abstract: 본 발명은 프로그램이 가능한 타이머에서 주기적인 타임아웃 인터럽트를 위한 플럭계수방법에 관한것으로, 프로그램이 가능한 타이머(3)가 프로세서(1) 및 프로세서 인터페이스 회로(2)와 연결되어 상기 타이머(3)의 내부에 3개의 레지스터로 구성된 MCR(4), OCR(8), BCR(11)에 의해 클럭을 계수하는 데 있어서, 상기 클럭계수방법은 먼저, 상기 타이머(3)가 초기화 되고나면(12) 클럭이 상승에지인가를 판단(13)하고, 상승에지이면 상기 OCR(10)이 0인가를 판단(14)하여 0이면 계수를 시작하고(15), 아니면 상기 OCR(10)이 1이고 BCR(11)이 0인가를 판단(16)하여 상기 타이머(3)를 타임아웃시키여 상기 단계(13)로 궤환하고(17), 그렇지 않으면 상기 BCR(11)이 0인가를 판단(18)하여 0이면 OCR(10)에서 1씩 감소시킨 값을 OCR(10)에 복사하고, MCR(6)를 BCR(11)에 복사하면서 상기 단계(13)로 궤환 고, 상기 BCR(11)이 0이 아니면 상기 BCR(11)에서 1씩 감소시킨 이 값을 BCR(11)에 저장하여 다시 상기 단계(13)이 되는 방법으로 구성된 상기 클럭계수방법은 프로그램된 계수단위에 1을 더한 수를 먼저 내림순으로 계수하고, 계수단위에 대한 계수가 끝나면 최대 계수치를 내림순으로 계수하는 2단계 계수과정으로서 계수를 수행하면, 계수단위(6)의 값을 변화시킴으로써 최대계수치를 계수하는 단위를 유연성 있게 조절하게 되어 다양한 시간 간격의 타임아웃 인터럽트를 발생시킬 수 있다.

公开(公告)号：KR100456630B1

公开(公告)日：2004-11-10

申请号：KR1020010078194

申请日：2001-12-11

Applicant: 한국전자통신연구원

Inventor： 박경 ,  모상만 ,  김용연

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: Disclosed herein is an interrupt redirection apparatus and method for inter-processor communication. The apparatus includes a plurality of ARM processors, a vectored interrupt controller, an interrupt command register, an interrupt data register for designating the contents of each interrupt, an interrupt signal generation unit, and a bus interface unit used for providing read and write accesses of both the interrupt command register and the interrupt data register. The vectored interrupt controller for receiving interrupts generated by hardware for performing a specific function under the control of each ARM processor and interrupts generated by peripheral hardware, and transferring each interrupt as each interrupt request signal to an ARM processor designated as a master processor. The interrupt command register designates targets and kinds of each interrupt to perform a function for receiving an interrupt redirection command and activating an interrupt request signal. The interrupt signal generation unit reads the contents and activates an interrupt request signal.

Abstract translation: 本文公开了一种用于处理器间通信的中断重定向装置和方法。 该设备包括多个ARM处理器，向量中断控制器，中断命令寄存器，用于指定每个中断的内容的中断数据寄存器，中断信号产生单元和总线接口单元，用于提供 中断命令寄存器和中断数据寄存器。 矢量中断控制器用于接收由硬件生成的中断，用于在每个ARM处理器的控制下执行特定功能以及由外设硬件产生的中断，并将每个中断作为每个中断请求信号传送给被指定为主处理器的ARM处理器。 中断命令寄存器指定每个中断的目标和种类，以执行接收中断重定向命令和激活中断请求信号的功能。 中断信号发生单元读取内容并激活中断请求信号。

公开(公告)号：KR100452325B1

公开(公告)日：2004-10-12

申请号：KR1020020082895

申请日：2002-12-23

Applicant: 한국전자통신연구원

Inventor： 박경 ,  김성남 ,  한종석 ,  모상만 ,  김명준 ,  임기욱

IPC: G06F13/00

Abstract: PURPOSE: An AMBA(Advanced Micro-controller Bus Architecture) bus based multiprocessor system to assign a processor number and be sequentially booted is provided to easily realize a shared-bus based multiprocessor system and enable the installation of a multiprocessor OS(Operating System) later on by assigning a processor ID and sequentially booting the multiprocessor. CONSTITUTION: The bus provides an address/control signal line, a read data signal line, and a write data signal line connecting the masters(210-1¯210-3) with other resources. A bus arbiter(230) generates an internal bus request signal depending on a bus enable signal by receiving the bus request signal from the master, controls a bus use permission of each bus master depending on the internal bus request signal, and outputs a bus user number of the master receiving the bus use permission. A multiprocessor supporting slave(280) provides the bus enable signal to the bus arbiter and receives/stores the bus user number from the bus arbiter.

Abstract translation: 目的：提供AMBA（高级微控制器总线架构）总线多处理器系统来分配处理器编号并被顺序引导，以便轻松实现基于共享总线的多处理器系统，并能够在稍后安装多处理器OS（操作系统） 通过分配处理器ID并依次引导多处理器。 构成：总线提供地址/控制信号线，读数据信号线和写数据信号线，将主设备（210-1和210-3）与其他资源连接起来。 总线仲裁器（230）根据总线使能信号通过接收来自主设备的总线请求信号产生内部总线请求信号，根据内部总线请求信号控制每个总线主设备的总线使用许可，并且输出总线用户 接收总线使用权限的主设备号码。 支持从设备（280）的多处理器向总线仲裁器提供总线使能信号，并从总线仲裁器接收/存储总线使用者号码。

公开(公告)号：KR100439184B1

公开(公告)日：2004-07-05

申请号：KR1020010084389

申请日：2001-12-24

Applicant: 한국전자통신연구원

Inventor： 한종석 ,  최용석 ,  모상만 ,  김용연

IPC: H04L12/861

Abstract: PURPOSE: A double word align writing packet buffer device having different size of two input ports is provided to generate and store packet headers by using an n-bit packet header generator or an n-bit local processor, and to store packet data in the buffer device by supplying a 2n-bit exclusive data path, thereby implementing fast transmission. CONSTITUTION: The first and the second input ports(412,413,414) have n-bit data width and 2n-bit data width. A packet send buffer(400) has the first and the second banks(401,402) where packets of the n-bit data width are stored in double word type. One pair of data multiplexers(403,404) select one of n-bit data inputted in the first input port(412) and n-bit data divided into 2 from the second input ports(413,414), and transmit the selected data to the first(401) or the second bank(402). One pair of address multiplexers(405,406) select an address inputted from the first and the second address input ports, and transmit the selected address to the first(401) or the second bank(402). A bank selector(422) selects the first(401) or the second bank(402) to activate the selected bank in response to a header writing or a data writing command.

Abstract translation: 目的：提供具有两个输入端口的不同大小的双字对齐写分组缓冲设备，以通过使用n比特分组报头生成器或n比特本地处理器生成并存储分组报头，并将分组数据存储在缓冲器中 装置通过提供2n位专用数据路径，从而实现快速传输。 构成：第一和第二输入端口（412,413,414）具有n位数据宽度和2n位数据宽度。 分组发送缓冲器（400）具有第一和第二组（401,402），其中n比特数据宽度的分组以双字类型存储。 一对数据多路复用器（403,404）选择在第一输入端口（412）中输入的n位数据和从第二输入端口（413,414）分解为2的n位数据中的一个，并将选择的数据发送到第一 401）或第二银行（402）。 一对地址复用器（405,406）选择从第一和第二地址输入端口输入的地址，并将选择的地址发送到第一（401）或第二存储体（402）。 存储体选择器（422）响应于首标写入或数据写入命令而选择第一（401）或第二存储体（402）以激活选定的存储体。

公开(公告)号：KR1020040056293A

公开(公告)日：2004-06-30

申请号：KR1020020082895

申请日：2002-12-23

Applicant: 한국전자통신연구원

Inventor： 박경 ,  김성남 ,  한종석 ,  모상만 ,  김명준 ,  임기욱

IPC: G06F13/00

Abstract: PURPOSE: An AMBA(Advanced Micro-controller Bus Architecture) bus based multiprocessor system to assign a processor number and be sequentially booted is provided to easily realize a shared-bus based multiprocessor system and enable the installation of a multiprocessor OS(Operating System) later on by assigning a processor ID and sequentially booting the multiprocessor. CONSTITUTION: The bus provides an address/control signal line, a read data signal line, and a write data signal line connecting the masters(210-1¯210-3) with other resources. A bus arbiter(230) generates an internal bus request signal depending on a bus enable signal by receiving the bus request signal from the master, controls a bus use permission of each bus master depending on the internal bus request signal, and outputs a bus user number of the master receiving the bus use permission. A multiprocessor supporting slave(280) provides the bus enable signal to the bus arbiter and receives/stores the bus user number from the bus arbiter.

Abstract translation: 目的：提供用于分配处理器号并被顺序启动的基于总线架构的AMBA（高级微控制器总线体系结构）总线系统，以便轻松实现基于共享总线的多处理器系统，并且可以稍后安装多处理器OS（操作系统） 通过分配处理器ID并顺序引导多处理器。 构成：总线提供地址/控制信号线，读数据信号线和连接主机（210-1〜210-3）与其他资源的写数据信号线。 总线仲裁器（230）通过从主机接收总线请求信号，根据总线使能信号产生内部总线请求信号，根据内部总线请求信号控制每个总线主机的总线使用许可，并输出总线用户 接收总线使用许可的主机号码。 多处理器支持从站（280）向总线仲裁器提供总线使能信号，并从总线仲裁器接收/存储总线用户号码。

公开(公告)号：KR1020040055194A

公开(公告)日：2004-06-26

申请号：KR1020020081819

申请日：2002-12-20

Applicant: 한국전자통신연구원

Inventor： 한종석 ,  최용석 ,  모상만 ,  김명준 ,  임기욱

IPC: G06F13/00

CPC classification number: G06F13/28

Abstract: PURPOSE: A system for controlling a data transfer protocol having a host bus interface is provided to support the optimal data transfer through the efficient use of a host interface bus and the proper distribution of a bus use rate, and smoothly process entire data transfer by controlling a host bus and the data transfer protocol. CONSTITUTION: The system includes a data transfer protocol controller(130), a transmitting/receiving command DMA(Direct Memory Access)(140), a transmitting-only data DMA(150), and a receiving-only data DMA(160). The data transfer protocol controller controls the data transfer protocol in a host channel adaptor having a PCI(Peripheral Component Interconnect)/PCI-X host bus interface(120) of a PCI/PCI-X host bus(110) as a host processor interface, and is equipped with a protocol processing master(131), an interrupt controller(132), and a protocol processing target(133). The system includes a command DMA request buffer(141), a command DMA response DMA buffer(142), a transmitting data DMA request buffer(151), a transmitting data DMA response buffer(152), a receiving data DMA request buffer(161), and a receiving data DMA response buffer(162).

Abstract translation: 目的：提供一种用于控制具有主机总线接口的数据传输协议的系统，以通过有效使用主机接口总线和正确分配总线使用率来支持最佳数据传输，并通过控制来平滑地处理整个数据传输 主机总线和数据传输协议。 构成：该系统包括数据传输协议控制器（130），发送/接收命令DMA（直接存储器访问）（140），只发送数据DMA（150）和仅接收数据DMA（160）。 数据传输协议控制器控制具有作为主处理器接口的PCI / PCI-X主机总线（110）的PCI（外围组件互连）/ PCI-X主机总线接口（120）的主机通道适配器中的数据传输协议 ，并配备有协议处理主控（131），中断控制器（132）和协议处理对象（133）。 该系统包括命令DMA请求缓冲器（141），命令DMA响应DMA缓冲器（142），发送数据DMA请求缓冲器（151），发送数据DMA响应缓冲器（152），接收数据DMA请求缓冲器（161） ）和接收数据DMA响应缓冲器（162）。

公开(公告)号：KR1020040037989A

公开(公告)日：2004-05-08

申请号：KR1020020066844

申请日：2002-10-31

Applicant: 한국전자통신연구원

Inventor： 김영우 ,  이재성 ,  박경 ,  모상만 ,  김용연 ,  김명준 ,  임기욱

IPC: G11C7/00

CPC classification number: G11C8/04

Abstract: PURPOSE: A first input first output(FIFO) memory circuit and a method for implementing the same are provided to improve the input and output speed of the FIFO memory by controlling the low speed memory. CONSTITUTION: A first input first output memory circuit includes a memory(100), a read pointer(400), a write pointer(300) and a memory controller(200). The memory(100) is composed of N number of memories. The read pointer(400) appoints the read address among the N number of memories and the write pointer(300) appoints the write address among the N number of memories. And, the memory controller(200) selects one memory among the N number of memories in response to the read/write address, generates a source clock signal by the divided n number of read/write clock signal and inputs and outputs the data by dividing the n number of read/write clock signal from the selected memory to the corresponding memory.

Abstract translation: 目的：提供第一输入第一输出（FIFO）存储器电路及其实现方法，以通过控制低速存储器来提高FIFO存储器的输入和输出速度。 构成：第一输入第一输出存储电路包括存储器（100），读指针（400），写指针（300）和存储器控制器（200）。 存储器（100）由N个存储器构成。 读指针（400）在N个存储器中指定读地址，写指针（300）在N个存储器中指定写地址。 并且，存储器控制器（200）响应于读/写地址在N个存储器中选择一个存储器，通过分割的n个读/写时钟信号产生源时钟信号，并通过分割来输入和输出数据 从所选择的存储器到对应的存储器的n个读/写时钟信号。

公开(公告)号：KR1020030054253A

公开(公告)日：2003-07-02

申请号：KR1020010084389

申请日：2001-12-24

Applicant: 한국전자통신연구원

Inventor： 한종석 ,  최용석 ,  모상만 ,  김용연

IPC: H04L12/861

CPC classification number: H04L49/9094 ,  H04L49/3018

Abstract: PURPOSE: A double word align writing packet buffer device having different size of two input ports is provided to generate and store packet headers by using an n-bit packet header generator or an n-bit local processor, and to store packet data in the buffer device by supplying a 2n-bit exclusive data path, thereby implementing fast transmission. CONSTITUTION: The first and the second input ports(412,413,414) have n-bit data width and 2n-bit data width. A packet send buffer(400) has the first and the second banks(401,402) where packets of the n-bit data width are stored in double word type. One pair of data multiplexers(403,404) select one of n-bit data inputted in the first input port(412) and n-bit data divided into 2 from the second input ports(413,414), and transmit the selected data to the first(401) or the second bank(402). One pair of address multiplexers(405,406) select an address inputted from the first and the second address input ports, and transmit the selected address to the first(401) or the second bank(402). A bank selector(422) selects the first(401) or the second bank(402) to activate the selected bank in response to a header writing or a data writing command.

Abstract translation: 目的：提供具有不同大小的两个输入端口的双字对齐写分组缓冲设备，以通过使用n位分组报头生成器或n位本地处理器来生成和存储分组报头，并将分组数据存储在缓冲器中 通过提供2n位独占数据路径，从而实现快速传输。 构成：第一和第二输入端口（412,413,414）具有n位数据宽度和2n位数据宽度。 分组发送缓冲器（400）具有第一和第二组（401,402），其中n位数据宽度的分组以双字类型存储。 一对数据多路复用器（403,404）从第二输入端口（413,414）中选择在第一输入端口（412）中输入的n位数据和被分成2位的数据之一，并将所选数据发送到第一（ 401）或第二存储体（402）。 一对地址多路复用器（405,406）选择从第一和第二地址输入端口输入的地址，并将选择的地址发送到第一（401）或第二存储体（402）。 存储体选择器（422）响应于标题写入或数据写入命令选择第一（401）或第二存储体（402）激活所选择的存储体。

公开(公告)号：KR100331027B1

公开(公告)日：2002-08-13

申请号：KR1019980049406

申请日：1998-11-18

Applicant: 한국전자통신연구원

Inventor： 모상만 ,  한우종 ,  윤석한

IPC: G06F9/46

Abstract: 본 발명은 디지털 컴퓨터 시스템에서 단일 신호 인터럽트 방식의 프로세서 (Single Signal Interrupted Processor)로부터 발생한 인터럽트 응답(Interrupt Acknowledge)의 제어에 관련되는 것으로서, 내부에 인터럽트 벡터 레지스터 (Interrupt Vector Register)를 내장한 인터럽트 응답 제어기(Interrupt Acknowledge Controller) 및 그 제어 방법을 제공하는데 그 목적이 있다.
본 발명에 따르면, 단일 신호 인터럽트 방식의 프로세서의 인터럽트 응답 제어 기능을 수행하는 인터럽트 응답 제어기에 있어서, 상기 프로세서의 인터럽트 응답에 대하여 인터럽트 벡터를 제공하고, 상기 프로세서가 읽기 및 쓰기를 수행할 수 있는 인터럽트 벡터 레지스터를 내부에 포함하는 것을 특징으로 하는 인터럽트 응답 제어기가 제공된다.

公开(公告)号：KR1020010063786A

公开(公告)日：2001-07-09

申请号：KR1019990061875

申请日：1999-12-24

Applicant: 한국전자통신연구원

Inventor： 모상만 ,  김성운 ,  한우종 ,  윤석한

IPC: G06F15/16

Abstract: PURPOSE: A cache controller having an interrupt controller and a method for controlling an interrupt are provided to control all sorts of interrupts informing all sorts of exceptions generated in a cache control process to a processor promptly and effectively. CONSTITUTION: A node bus interface(210) is connected to a node bus between a node bus being connected to a processor and an interconnection network. An interconnection network interface(220) is connected to the interconnection network. Bus buffers(211, 212, 213, 214) are connected to the node bus interface. Network buffers(221, 222, 223, 224) are connected to the interconnection network interface(220). A cache control logic(200) is connected to the bus buffers(211, 212, 213, 214) and the network buffers(221, 222, 223, 224). A cache(tag memory, data memory) is accessed by the cache control logic(200). An interrupt control unit(230) is connected to the cache control logic(200) and the node bus interface(210) for informing exception contents generated in a cache control process to a processor as an interrupt. The interrupt control unit(230) includes an interrupt control/status register(ICSR)(231) for the interrupt control.

Abstract translation: 目的：提供具有中断控制器和用于控制中断的方法的高速缓存控制器，用于控制各种中断，将快速缓存控制过程中产生的各种异常通知给处理器，并迅速有效地进行处理。 构成：节点总线接口（210）连接到连接到处理器的节点总线和互连网络之间的节点总线。 互连网络接口（220）连接到互连网络。 总线缓冲器（211,212,213,214）连接到节点总线接口。 网络缓冲器（221,222,223,224）连接到互连网络接口（220）。 缓存控制逻辑（200）连接到总线缓冲器（211,212,213,214）和网络缓冲器（221,222,223,224）。 缓存（标签存储器，数据存储器）由高速缓存控制逻辑（200）访问。 中断控制单元（230）连接到高速缓存控制逻辑（200）和节点总线接口（210），用于将高速缓存控制处理中生成的异常内容通知给处理器作为中断。 中断控制单元（230）包括用于中断控制的中断控制/状态寄存器（ICSR）（231）。