Abstract:
PURPOSE: A self aligned field effect transistor structure is provided to improve operation speed by removing a photoresist residue between a source/drain and a substrate and reducing contact resistance between them. CONSTITUTION: An active region(122) is formed on a substrate(110). An uneven gate insulation pattern(142) is formed on the active region. The gate insulation pattern comprises a side wall and a bottom wall. A gate electrode(152) is formed inside the gate insulation pattern. A source/drain(154) is formed on the substrate adjacent to the gate insulation pattern.
Abstract:
PURPOSE: A manufacturing method of a semiconductor device is provided to obtain a T-shape gate electrode including a short leg part a low resistance. CONSTITUTION: A first photosensitive pattern is formed on a substrate(100). A second photosensitive pattern(122) exposing a part of the first photosensitive pattern is formed. A third photosensitive pattern with a first opening(134), which exposes a second photosensitive layer that is around the first photosensitive layer, is formed. The first photosensitive pattern exposed by the first opening is removed. A second opening(124) which exposes the substrate is formed. A T-shape gate electrode(146) with a leg part(142) and a head part(144), which fill the second opening, is formed.
Abstract:
본 발명은 유연한 기판을 세정하기 위한 새로운 세정 방법에 관한 것이다. 본 발명의 플렉시블 기판의 세정 방법은 플렉시블 기판을 넣고 플렉시블 기판의 양쪽 주면 상에 각각 위치하는 회전식 제1 롤러를 이용해 플렉시블 기판의 양쪽 주면에 부착된 불순물을 점착력을 이용하여 떼어내는 단계와, 제1 롤러에 비해 상대적으로 큰 점착력을 가진 회전식 제2 롤러를 이용하여 제1 롤러로부터 제2 롤러로 불순물을 전사시켜 제거하는 단계를 포함한다. 플렉시블 기판, 세정, 플렉시블 소자, 플렉시블 디스플레이
Abstract:
An organic light emitting diode device is provided to increase a luminous efficiency through a balanced injection of charges and to ensure excellent durability and a long life. An organic light emitting diode device includes a substrate(10), an anode(20) formed on the substrate, a first organic thin film layer(A) formed on the anode, an organic light emitting layer(50) formed on the first organic thin film layer, a second organic thin film layer(B) formed on the organic light emitting layer, and a cathode(90) formed on the second organic thin film layer. The first organic thin film layer and the second organic thin film layer are mono-layered or multi-layered, respectively. At least a part of the first organic thin film layer and the second organic thin film layer is doped or stacked with an insulating material.
Abstract:
A self-aligned organic FET(field effect transistor) is provided to reduce parasitic capacitance by using a photosensitive polymer thin film as a gate electrode and by preventing a gate electrode from overlapping a source/drain electrode. A gate electrode is formed on a substrate(201) by using a photosensitive polymer thin film. A gate insulation layer(203) is formed on the substrate and the gate electrode. A source electrode(206) and a drain electrode(207) are formed on the gate insulation layer at both sides of a channel region in a manner that doesn't overlap the gate electrode. An organic semiconductor layer is formed on the gate insulation layer in the channel region. The gate insulation layer can be made of an organic or inorganic material with transparency. A transparent electrode can be used as the source electrode and the drain electrode.
Abstract:
본 발명은 유기 박막 트랜지스터 소자 제작에 사용될 수 있는 유기 반도체 물질인 펜타센(pentacene) 전구체과 펜타센, 이들의 제조방법 및 이들을 이용한 유기 박막 트랜지스터에 관한 것이다. 본 발명에 따른 펜타센 전구체는 방향족 아진화합물과 벤진 유사체를 딜스-알더(Diels-Alder) 반응시켜 합성되며, 이렇게 얻어진 펜타센 전구체를 열분해(pyrolysis)하여 펜타센을 합성한다. 펜타센 전구체 자체는 스핀 코팅과 같은 습식 공정을 이용하여 유기 박막 트랜지스터용 반도체층을 형성할 수 있으며, 또한 펜타센은 진공 증착과 같은 건식 공정에 의해 반도체층을 형성할 수 있다. 펜타센, 펜타센 전구체, 딜스-알더 반응, 유기 반도체, 유기 박막 트랜지스터 소자
Abstract:
A method for fabricating an organic thin film transistor is provided to minimize deterioration of an organic layer by minimizing substrate heating effect. A source gas is absorbed onto a surface of a substrate by implanting the source gas into an inside of a reactor(S10). A source gas purging process is performed to purge the source gas absorbed onto the substrate or the remaining source gas within the reactor(S20). An inorganic oxide layer is formed by supplying an oxygen gas and generating plasma(S30). The oxygen gas and the plasma are intercepted(S40). A purge gas supply process is performed to purge the reactive residues and the remaining gas by supplying the purge gas(S50).
Abstract:
본 발명은 유기물 전도체막의 미세 패터닝 방법, 이로부터 형성된 미세 패턴화된 유기물 전도체막 및 미세 패턴화된 유기물 전도체막을 적용시킨 유기 박막 트랜지스터에 관한 것이다. 본 발명에 따른 유기물 전도체의 미세 패터닝 방법은 노광조건을 제어하고, 리프트 오프 방법을 적용하여 유기물의 특성에 영향을 주지 않으면서 미세 패터닝이 가능한 방법을 제공하는 것이다. 유기물, 미세 패터닝, 감광막, 리프트 오프