62.
    发明专利
    未知

    公开(公告)号:DE10162900C1

    公开(公告)日:2003-07-31

    申请号:DE10162900

    申请日:2001-12-20

    Abstract: The invention relates to a method for fabricating low-resistance electrodes in trench capacitors, and includes steps of: providing a wafer; producing trenches in the wafer; introducing the wafer into an electrolyte solution including a salt of an electrically conductive material; and electrically contact-connecting the wafer and applying a voltage between the wafer and a counterelectrode configured in the electrolyte solution to electrodeposit at least sections of the electrically conductive material in the trenches. The electrodeposition of the electrode material enables a uniform layer thickness along all regions of the trench wall.

    64.
    发明专利
    未知

    公开(公告)号:DE10139827A1

    公开(公告)日:2003-03-13

    申请号:DE10139827

    申请日:2001-08-14

    Abstract: The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.

    65.
    发明专利
    未知

    公开(公告)号:DE10138981A1

    公开(公告)日:2003-03-06

    申请号:DE10138981

    申请日:2001-08-08

    Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.

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