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    2.
    发明专利
    未知

    公开(公告)号：DE102004044678B4

    公开(公告)日：2006-08-31

    申请号：DE102004044678

    申请日：2004-09-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KUNDALGURKI SRIVATSA ,  SCHUPKE KRISTIN ,  MANGER DIRK ,  SCHLOESSER TILL ,  MOLL PETER

    IPC: H01L21/8242

    Abstract: In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).

    Production of a trench capacitor comprises a preparing a substrate having a surface in which a trench is formed and having an upper region, a lower region and a side wall
    7.
    发明专利
    Production of a trench capacitor comprises a preparing a substrate having a surface in which a trench is formed and having an upper region, a lower region and a side wall 未知

    公开(公告)号：DE10143283C1

    公开(公告)日：2002-12-12

    申请号：DE10143283

    申请日：2001-09-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FOERSTER MATTHIAS ,  MOLL ANETT ,  MORGENSCHWEIS ANJA ,  SACHSE JENS-UWE ,  SCHUPKE KRISTIN

    IPC: H01L21/02 ,  H01L21/8242

    Abstract: Production of a trench capacitor comprises a preparing a substrate having a surface in which a trench is formed and having an upper region, a lower region and a sidewall; inserting a dopant through the trench side wall in the lower region of the trench. Method also involves forming a mask layer on the trench side wall of the lower region of the trench; depositing nanocrystals on the mask layers so that the crystals cover a first part of the mask layer and expose a second part of the mask layer; etching the mask layer to expose the trench side wall; etching the substrate in the lower region of trench using a structured mask layer; removing the structured mask layer (110) by etching; forming an insulation layer on the trench side wall; depositing a conducting trench filling in the trench on the insulation layer as inner capacitor electrode; and forming a transistor which is connected to the conducting trench filling to control the trench capacitor. Preferred Features: An insulation collar is produced in the upper region of the trench on the side wall before the side wall is roughened. The mask layer is formed using LPCVD nitride deposition.

    8.
    发明专利
    未知

    公开(公告)号：DE102005025951A1

    公开(公告)日：2006-01-05

    申请号：DE102005025951

    申请日：2005-06-06

    Applicant: INFINEON TECHNOLOGIES AG ,  NANYA TECHNOLOGY CORP KUEISHAN

    Inventor： GOLDBACH MATTHIAS ,  JAKUBOWSKI FRANK ,  KOEPE RALF ,  LAY CHAO-WEN ,  SCHUPKE KRISTIN ,  SCHMIDT MICHAEL ,  HUANG CHENG CHIH

    IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78 ,  H01L31/062

    Abstract: A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.

    10.
    发明专利
    未知

    公开(公告)号：DE10202140A1

    公开(公告)日：2003-08-07

    申请号：DE10202140

    申请日：2002-01-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： POPP MARTIN ,  TEMMLER DIETMAR ,  SCHUPKE KRISTIN ,  SCHILLING UWE

    IPC: H01L21/20 ,  H01L21/8242 ,  H01L27/108 ,  B81C1/00

    Abstract: A semiconductor component having a cavity is produced by: (i) forming a cavity in a monocrystalline silicon substrate (1), and covering walls of the cavity with a cover layer at least in an upper end region of the cavity; (ii) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (iiii) growing the covering layer only on the silicon surface. Production of a semiconductor component having a cavity comprises: (a) providing a monocrystalline silicon substrate having a silicon surface; (b) forming a cavity in the silicon substrate and covering walls of the cavity, with a cover layer at least in an upper end region of the cavity; (c) depositing a covering layer on the silicon substrate with a selective epitaxial process; and (d) growing the covering layer only on the silicon surface to cover the cavity with the covering layer, and to form a covered cavity in the monocrystalline silicon substrate.

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