公开(公告)号：DE10128326C1

公开(公告)日：2003-02-13

申请号：DE10128326

申请日：2001-06-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  GUTSCHE MARTIN ,  SEIDL HARALD

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench capacitor is fabricated by forming a trench (5) in a substrate (1), providing a lower capacitor electrode which adjoins a wall of the trench in a lower trench region, and providing a storage dielectric and an upper capacitor electrode. Fabrication of a trench capacitor comprises: (i) forming a trench in a substrate; (ii) providing a lower capacitor electrode which adjoins a wall of the trench in a lower trench region; (iii) providing a storage dielectric on the lower capacity electrode; (iv) providing an upper capacitor electrode on the storage dielectric, the upper capacitor electrode having metal-containing layers deposited one on top of another; and (v) conditioning the metal-containing layers after they have been deposited and before a next metal-containing layer is deposited.

公开(公告)号：DE10128718A1

公开(公告)日：2003-01-02

申请号：DE10128718

申请日：2001-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  ALSMEIER JOHANN

IPC: H01L21/8242 ,  H01L27/108

Abstract: A memory cell has a selection transistor and a trench capacitor. An upper capacitor electrode of the trench capacitor, in the region of an insulating collar, has a metallic section, and that section of the upper electrode that makes contact with a storage dielectric is of a non-metallic form, in particular containing polysilicon. A buried strap, which connects the upper electrode to the select transistor, is of a non-metallic form, in particular formed of polysilicon.

公开(公告)号：DE10115912A1

公开(公告)日：2002-10-17

申请号：DE10115912

申请日：2001-03-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  MOL PETER ,  SEIDL HARALD ,  GUTSCHE MARTIN

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/8242 ,  H01L21/027 ,  H01L21/32 ,  H01L21/3213 ,  B81C1/00

Abstract: The invention relates to a lithographic method for removing a thin masking layer, particularly a Si3N4 layer on a side of a recess in a semi-conductor arrangement. According to the invention, an ion beam is orientated in an inclined manner at a certain angle towards the recess, enabling the thin masking layer to be removed in the regions exposed to the beams.

公开(公告)号：DE10101526A1

公开(公告)日：2002-08-01

申请号：DE10101526

申请日：2001-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  GUTSCHE MARTIN ,  HECHT THOMAS ,  LEONHARDT MATTHIAS

IPC: H01L21/8242 ,  H01L27/108

Abstract: The dielectric layer (70) is applied by depositing silicon nitride and/or silicon oxynitride layers. This is followed by thermal treatment in a nitrogen-containing gas, with subsequent oxidation. An independent claim is included for the associated method.

公开(公告)号：DE10038378A1

公开(公告)日：2002-02-28

申请号：DE10038378

申请日：2000-08-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN ,  GSCHWANDTNER ALEXANDER

IPC: H01L21/02 ,  H01L21/8242

公开(公告)号：DE19958904C2

公开(公告)日：2002-01-24

申请号：DE19958904

申请日：1999-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  B81C1/00

Abstract: The method is for producing a hard mask on a substrate, and in particular, on a primary area of a semiconductor substrate. The method includes the following steps: forming a first hard mask layer on the substrate; forming at least one additional hard mask layer on the first hard mask layer; structuring the additional hard mask layer in such a way that an area of the first hard mask layer is exposed; and structuring the first hard mask layer while using the additional hard mask layer as a mask so that an area of the substrate is exposed. Additional hard mask layers can be formed on the first hard mask layer. These hard mask layers are successively structured while using at least one overlying hard mask layer as a mask, until the area of the substrate is exposed.

公开(公告)号：DE19958904A1

公开(公告)日：2001-06-21

申请号：DE19958904

申请日：1999-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GUTSCHE MARTIN

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  B81C1/00

Abstract: The invention relates to a method for producing a hard mask on a substrate (10) and, in particular, on a primary area of a semiconductor substrate. The inventive method comprises the following steps: forming a first hard mask layer (n) on the substrate (10); forming at least one additional hard mask layer (n-1) on the first hard mask layer (n); structuring the additional hard mask layer (n-1) in such a way that an area of the first hard mask layer (n) is exposed, and; structuring the first hard mask layer (n) while using the additional hard mask layer (n-1) as a mask so that an area of the substrate (10) is exposed. Additional hard mask layers (n-1, n-2, ..., 1) can be formed on the first hard mask layer (n), which are successively structured while using at least one overlying hard mask layer as a mask, until the area of the substrate (10) is exposed.