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公开(公告)号:DE10142580A1
公开(公告)日:2003-03-27
申请号:DE10142580
申请日:2001-08-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SEIDL HARALD , GUTSCHE MARTIN , HECHT THOMAS , LEONHARDT MATTHIAS , SCHROEDER UWE
IPC: H01L21/8242
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公开(公告)号:DE10142580B4
公开(公告)日:2006-07-13
申请号:DE10142580
申请日:2001-08-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SEIDL HARALD , GUTSCHE MARTIN , HECHT THOMAS , LEONHARDT MATTHIAS , SCHROEDER UWE
IPC: H01L21/8242
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公开(公告)号:DE10130936B4
公开(公告)日:2004-04-29
申请号:DE10130936
申请日:2001-06-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: REISINGER HANS , GUTSCHE MARTIN , SCHUPKE KRISTIN , JAKSCHIK STEFAN , LEONHARDT MATTHIAS , SEIDL HARALD , SCHROEDER UWE , HECHT THOMAS
IPC: C23C16/02 , C23C16/44 , C23C16/455 , H01L21/306 , H01L21/316 , H01L21/8242 , C30B29/16
Abstract: The present invention provides a method for fabricating a semiconductor component having a substrate (1) and a dielectric layer (70) provided on or in the substrate (1), the dielectric layer (7) being deposited in alternating self-limiting monolayer form, in the form of at least two different precursors, by means of an ALD process. There is provision for conditioning of the surface of the substrate (1) prior to the deposition of a first monolayer of a first precursor with respect to a reactive ligand of the first precursor.
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公开(公告)号:DE10130936A1
公开(公告)日:2003-01-16
申请号:DE10130936
申请日:2001-06-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: REISINGER HANS , GUTSCHE MARTIN , SCHUPKE KRISTIN , JAKSCHIK STEFAN , LEONHARDT MATTHIAS , SEIDL HARALD , SCHROEDER UWE , HECHT THOMAS
IPC: C23C16/02 , C23C16/44 , C23C16/455 , H01L21/306 , H01L21/316 , H01L21/8242 , C30B29/16
Abstract: Process for producing a semiconductor element having a dielectric layer (70) deposited on a substrate (1) in a monolayer alternately in the form of at least two different precursors using an ALD process comprises conditioning of the surface of the substrate before deposition of the first monolayer of a first precursor with regard to a reactive ligand of the first precursor. Preferred Features: A silicon oxide layer is removed from the surface of the substrate during conditioning. OH-, H- or H2-conditioning of the surface of the substrate is carried out.
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公开(公告)号:DE10101526A1
公开(公告)日:2002-08-01
申请号:DE10101526
申请日:2001-01-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SEIDL HARALD , GUTSCHE MARTIN , HECHT THOMAS , LEONHARDT MATTHIAS
IPC: H01L21/8242 , H01L27/108
Abstract: The dielectric layer (70) is applied by depositing silicon nitride and/or silicon oxynitride layers. This is followed by thermal treatment in a nitrogen-containing gas, with subsequent oxidation. An independent claim is included for the associated method.
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公开(公告)号:DE10141084A1
公开(公告)日:2002-11-28
申请号:DE10141084
申请日:2001-08-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor: HECHT THOMAS , GUTSCHE MARTIN , SEIDL HARALD , LEONHARDT MATTHIAS
IPC: C23C16/44 , C23C16/455 , C23C16/458 , C23C16/54
Abstract: Apparatus for depositing layers having atomic thickness on a substrate comprises a chamber with a first chamber region in which a first layer is deposited on a substrate, a second chamber region in which a second layer is deposited on the first layer and a transport system for transporting the substrate. The first and second chamber regions are separated by a chamber wall. Apparatus for depositing layers having atomic thickness on a substrate (5) comprises a chamber (10) with a first chamber region (15), into which a first process gas (20) is introduced to deposit a first layer (25) on the substrate, and a second chamber region (30), into which a second process gas (35) is introduced to deposit a second layer (40) on the first layer; and a transport system (45) to transport the substrates. A chamber wall (55) is arranged between the first chamber region and the second chamber region to separate the chamber regions. An Independent claim is also included for a process for depositing layers having atomic thickness on a substrate. Preferred Features: The chamber wall has a recess so that a substrate can pass through the chamber wall. A third chamber region (65) is arranged between the first chamber region and the second chamber region to separate the first and second chamber regions.
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