公开(公告)号：DE102006002940A1

公开(公告)日：2006-10-19

申请号：DE102006002940

申请日：2006-01-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： KUDELKA STEPHAN ,  SETTLEMEYER KENNETH ,  TEWS HELMUT

IPC: H01L21/8242

公开(公告)号：DE10226914B4

公开(公告)日：2006-03-02

申请号：DE10226914

申请日：2002-06-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: A method for fabricating a spacer structure includes: forming a gate insulation layer having a gate deposition-inhibiting layer, a gate layer and a covering deposition-inhibiting layer on a semiconductor substrate, and patterning the gate layer and the covering deposition-inhibiting layer in order to form gate stacks. An insulation layer is deposited selectively using the deposition-inhibiting layers, thereby permitting highly accurate formation of the spacer structure.

公开(公告)号：DE10345455A1

公开(公告)日：2005-05-04

申请号：DE10345455

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  FEHLHABER RODGER

IPC: H01L21/033 ,  H01L21/308 ,  G03F7/00

Abstract: An interconnect connection structure having first and second interconnects and multiple connection elements that electrically connect the first interconnect to the second interconnect is described. The multiple connection elements are formed laterally in a lateral region of the first and second interconnects relative to an overlay orientation of the interconnects. A central region may be free of connection elements so that electro-migration properties of the connection structure are improved and the current-carrying capacity is increased.

公开(公告)号：AU2003289828A8

公开(公告)日：2004-07-14

申请号：AU2003289828

申请日：2003-12-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  FEHLHABER RODGER

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

公开(公告)号：DE10350354A1

公开(公告)日：2004-05-27

申请号：DE10350354

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GLUSCHENKOV OLEG ,  TEWS HELMUT

IPC: H01L21/316 ,  H01L21/314 ,  H01L21/321 ,  H01L29/78 ,  H01L21/336

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

公开(公告)号：DE10341576A1

公开(公告)日：2004-03-18

申请号：DE10341576

申请日：2003-09-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AKATSU HIROYUKI ,  GLUSCHENKOV OLEG ,  PARKINSON PORSHIA SHANE ,  RAMACHANDRAN RAVIKUMAR ,  SETTLEMYER KENNETH T ,  TEWS HELMUT

IPC: H01L21/20 ,  H01L21/8242

Abstract: Microelectronic structure is manufactured by: (i) forming set of openings in surface of substrate (10); (ii) forming film stack having layers on each sidewall of openings; (iii) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (iv) thermally nitriding silicon layer on upper portion of structure. Fabrication of microelectronic structure comprises: (a) forming set of openings in surface of substrate; (b) forming film stack having layers on each sidewall of openings; (c) exposing oxide layer on lower portion of structure and silicon layer on upper portion of structure; and (d) thermally nitriding silicon layer on upper portion of structure to form nitrided silicon layer having first thickness limited through reaction kinetics and less than barrier thickness. The openings have sidewalls that extend to a common bottom wall. The layers include nitride diffusion barrier layer having a barrier thickness and silicon layer deposited after the barrier layer.

公开(公告)号：DE10231965A1

公开(公告)日：2004-02-12

申请号：DE10231965

申请日：2002-07-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEWS HELMUT ,  BARTH HANS-JOACHIM

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423

公开(公告)号：DE10217876A1

公开(公告)日：2003-11-06

申请号：DE10217876

申请日：2002-04-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTH HANS-JOACHIM ,  TEWS HELMUT

IPC: C25D5/50 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768

Abstract: The invention relates to a method for fabricating thin metal-containing layers ( 5 C) having low electrical resistance, firstly a metal-containing starting layer ( 5 A) having a first grain size being formed on a carrier material ( 2 ). Afterwards, a locally delimited thermal region (W) is produced and moved in the metal-containing starting layer ( 5 A) in such a way that a recrystallization of the metal-containing starting layer ( 5 A) is carried out for the purpose of producing the metal-containing layer ( 5 C) having a second grain size, which is enlarged with respect to the first grain size. A metal-containing layer having improved electrical properties is obtained in this way.