公开(公告)号：AU1429997A

公开(公告)日：1997-07-14

申请号：AU1429997

申请日：1996-12-10

Applicant: INTEL CORP

Inventor： DULONG CAROLE ,  PELEG ALEXANDER D ,  MENNEMEIER LARRY M

IPC: G06T1/20 ,  G06F15/00

Abstract: A computer system which manipulates audio and video signals. A multimedia input device which generates an audio and/or video signal is coupled to a processor. The processor is also coupled to a storage device upon which a decompression routine is stored, the decompression routine including a transposition routine. The transposition routine manipulates data elements associated with the audio or video signal in transposing an array of n rows of a plurality of data elements. The transposition routine causes the processor to interleave data elements from a first row with data elements from a second row to generate a first result. Data elements from a third row are interleaved with data elements from a fourth row to generate a second result. Then, data elements from the first result are interleaved with data elements from the second result to generate a third result.\!

公开(公告)号：AU1345597A

公开(公告)日：1997-07-14

申请号：AU1345597

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA RAMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00 ,  G06F7/48 ,  G06F12/00 ,  G06F12/02

公开(公告)号：AU1345197A

公开(公告)日：1997-07-14

申请号：AU1345197

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： BISTRY DAVID ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  DULONG CAROLE ,  KOWASHI EIICHI ,  MITTAL MILLIND ,  EITAN BENNY

IPC: G06F9/30 ,  G06F9/302 ,  G06F7/22

Abstract: An apparatus (e.g. a microarchitecture of a microprocessor) comprising a plurality of tags associated with a first storage area indicating that locations in the first storage area are either empty or non-empty responsive to execution of floating point instructions which modify data contained in the first storage area. A first circuit is coupled to the plurality of tags which sets only the plurality of tags to an empty state responsive to receipt of a first instruction. The first instruction indicates termination of execution of instructions which operate upon the packed data stored in the first storage area. The apparatus further comprises a second circuit coupled to the plurality of tags for setting the plurality of tags to a non-empty state responsive to receipt of a second instruction (or instructions). The second instruction specifies an operation upon packed data stored in the first storage area. The second circuit further sets the plurality of tags to indicate execution of instructions which operate upon the packed data. This apparatus advantageously provides a architecture (e.g. a microarchitecture for a microprocessor) for clearing the packed data state at the end of executed blocks of packed data instructions to leave the floating point state in a clear condition for subsequent operations (e.g. blocks of executed floating point instructions).

公开(公告)号：AU1025197A

公开(公告)日：1997-07-14

申请号：AU1025197

申请日：1996-11-25

Applicant: INTEL CORP

Inventor： MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  GLEW ANDREW F ,  DULONG CAROLE ,  KOWASHI EIICHI ,  MITTAL MILLIND ,  WITT WOLF ,  EITAN BENNY

IPC: G06F13/16 ,  G06F12/02

Abstract: A method for transferring packed data including the steps of first receiving an instruction from a set of instructions for transferring packed data between an extended register file and either an integer register file or a memory. In one embodiment, the extended register file includes eight registers, with each of the extended register storing up to sixty-four data bits. The integer register file also includes eight registers. The instruction includes an opcode that specifies a direction of the transfer with respect to the extended register file. The instructions are encoded in an instruction format having up to three bits addressing a destination operand and up to three bits addressing a source operand. The instruction is then translated to determine a direction of the transfer, a size of said packed data to be transferred, the address of the destination operand, and the address of the source operand. The instruction decoded by a decoder unit previously designed to decode the instruction format used to encode the set of instructions. In response to receiving the instruction, the packed data is transferred between the extended register file and either the integer register file or the memory, pursuant to the specifications of the translated instruction.

公开(公告)号：CA2230108A1

公开(公告)日：1997-03-06

申请号：CA2230108

申请日：1996-08-07

Applicant: INTEL CORP

Inventor： WITT WOLF ,  BUI TUAN H ,  KOWASHI EIICHI ,  PELEG ALEXANDER D ,  LIN DERRICK CHU ,  BINDAL AHMET ,  DULONG CAROLE ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  FISCHER STEPHEN A ,  EITAN BENNY

IPC: G06F7/53 ,  G06F5/00 ,  G06F7/00 ,  G06F7/48 ,  G06F7/483 ,  G06F7/49 ,  G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20 ,  G06F15/76 ,  G06F15/80