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    2.
    发明专利
    未知

    公开(公告)号：DE112006003575T5

    公开(公告)日：2008-11-06

    申请号：DE112006003575

    申请日：2006-12-18

    Applicant: INTEL CORP

    Inventor： MILSTREY ROBERT ,  NAVEH ALON ,  GEORGE VARGHESE ,  JAHAGIRDAR SANJEEV ,  FISCHER STEPHEN A ,  CONRAD JOHN B

    IPC: G06F1/32

    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

    Cache line flush instruction and method
    3.
    发明专利
    Cache line flush instruction and method 未知

    公开(公告)号：GB2401227A

    公开(公告)日：2004-11-03

    申请号：GB0415931

    申请日：2000-12-28

    Applicant: INTEL CORP

    Inventor： PALANCA SALVADOR ,  FISCHER STEPHEN A ,  MAIYURAN SUBRAMANIAM

    IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0811

    Abstract: A cache line flush instruction (CPFLUSH) micro-architectural implementation process and system allow a processor to flush a cache line associated with a linear memory address from all caches in a coherency domain. A cache controller receives a cache flush instruction having an associated memory address and performs a self snoop to flush the cache line corresponding to the memory address from its cache memory. The cache controller then generates a bus transaction regardless of whether the cache line was present in its cache memory and regardless of the state of the cache line if present. The bus transaction includes the memory address and causes other instances of the memory address in other caches of the coherency domain to be flushed or invalidated.

    Cache line flush micro-architectural implementation method and system
    4.
    发明专利
    Cache line flush micro-architectural implementation method and system 未知

    公开(公告)号：GB2374962A

    公开(公告)日：2002-10-30

    申请号：GB0217123

    申请日：2000-12-28

    Applicant: INTEL CORP

    Inventor： PALANCA SALVADOR ,  FISCHER STEPHEN A ,  MAIYURAN SUBRAMANIAM

    IPC: G06F12/08

    Abstract: A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

    Processor serial number with user controllable read access disabling
    5.
    发明专利
    Processor serial number with user controllable read access disabling 未知

    公开(公告)号：AU2615300A

    公开(公告)日：2000-08-07

    申请号：AU2615300

    申请日：2000-01-14

    Applicant: INTEL CORP

    Inventor： FISCHER STEPHEN A ,  THAKKAR SHREEKANT S ,  SULLIVAN ROBERT R JR ,  POLLACK FREDERICK J

    IPC: G06F11/00 ,  G06F21/00 ,  G06F1/00

    Abstract: A software method of setting a state in a processor regarding whether a processor number encoded in the processor will be available for reading is described. The method comprises prompting the user to enter an indication whether the processor number should be available for reading by a program. Then, setting a state to inhibit the processor number from being read by a program if the indication indicates that the processor number should not be available for reading by the program. For one embodiment, the method further includes testing the indication if a request for the processor number is received, and releasing the processor number if the indication indicates that the processor number is available.

    A cache line flush instruction and method, apparatus, and system for implementing the same.
    7.
    发明专利
    A cache line flush instruction and method, apparatus, and system for implementing the same. 未知

    公开(公告)号：ZA200205198B

    公开(公告)日：2004-02-03

    申请号：ZA200205198

    申请日：2002-06-27

    Applicant: INTEL CORP

    Inventor： PALANCA SALVADOR ,  FISCHER STEPHEN A ,  MAIYURAN SUBRAMANIAM

    IPC: G06F12/08 ,  G06F

    Abstract: A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

    A cache line flush instruction and method, apparatus, and system for implementing the same.
    8.
    发明专利
    A cache line flush instruction and method, apparatus, and system for implementing the same. 未知

    公开(公告)号：HK1049217A1

    公开(公告)日：2003-05-02

    申请号：HK03101290

    申请日：2003-02-20

    Applicant: INTEL CORP

    Inventor： PALANCA SALVADOR ,  FISCHER STEPHEN A ,  MAIYURAN SUBRAMANIAM

    IPC: G06F12/08 ,  G06F

    Abstract: A system and method for flushing a cache line associated with a linear memory address from all caches in the coherency domain. A cache controller receives a memory address, and determines whether the memory address is stored within the closest cache memory in the coherency domain. If a cache line stores the memory address, it is flushed from the cache. The flush instruction is allocated to a write-combining buffer within the cache controller. The write-combining buffer transmits the information to the bus controller. The bus controller locates instances of the memory address stored within external and intel cache memories within the coherency domain; these instances are flushed. The flush instruction can then be evicted from the write-combining buffer. Control bits may be used to indicate whether a write-combining buffer is allocated to the flush instruction, whether the memory address is stored within the closest cache memory, and whether the flush instruction should be evicted from the write-combining buffer.

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