公开(公告)号：HK1094744A1

公开(公告)日：2007-04-04

申请号：HK07102030

申请日：2007-02-22

Applicant: INTERDIGITAL TECH CORP

Inventor： CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  MORABITO JOSEPH T

IPC: H03M20100101 ,  H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H04B1/69 ,  H04B7/155 ,  H04B7/208 ,  H04B7/212 ,  H04B7/216 ,  H04B7/26 ,  H04J3/00 ,  H04J3/02 ,  H04L20100101 ,  H04L1/00 ,  H04Q11/00 ,  H04W88/02 ,  H04W88/08

Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping. The bits are directly read from the determined first interleaver buffer addresses and written to the physical channel buffer addresses.

公开(公告)号：AU2006283502A1

公开(公告)日：2007-03-01

申请号：AU2006283502

申请日：2006-08-22

Applicant: INTERDIGITAL TECH CORP

Inventor： MARINIER PAUL ,  CASTOR DOUGLAS R

IPC: H04B7/216 ,  H04B17/40

公开(公告)号：NO20065601L

公开(公告)日：2007-01-31

申请号：NO20065601

申请日：2006-12-05

Applicant: INTERDIGITAL TECH CORP

Inventor： CASTOR DOUGLAS R ,  LEVI ALAN M ,  DESAI BINISH P

IPC: H04L12/66 ,  H04B7/00 ,  H04J11/00 ,  H04L12/56 ,  H04W28/14

Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

公开(公告)号：AT350822T

公开(公告)日：2007-01-15

申请号：AT03719734

申请日：2003-04-15

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  STARSINIC MICHAEL F ,  BASS DAVID S ,  DESAI BINISH ,  LEVI ALAN M ,  MCCLELLAN GEORGE W ,  CASTOR DOUGLAS R

IPC: H04J1/00 ,  H04B1/40 ,  H04B1/707 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：CA2575114A1

公开(公告)日：2006-02-23

申请号：CA2575114

申请日：2005-07-19

Applicant: INTERDIGITAL TECH CORP

Inventor： HACKETT WILLIAM C ,  DIFAZIO ROBERT A ,  REZNIK ALEXANDER ,  CASTOR DOUGLAS R ,  HEPLER EDWARD L ,  ZEIRA ARIELA ,  GAZDA ROBERT G ,  KAEWELL JOHN DAVID JR

IPC: H04B7/216 ,  H04B1/707 ,  H04W88/02

Abstract: A wireless transmit/receive unit (WTRU) for processing code division multiple access (CDMA) signals. The WTRU includes a modem host and a high speed downlink packet access (HSDPA) co-processor, which communicate over a plurality of customizable interfaces. The modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU as a whole such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.

公开(公告)号：NO20044923L

公开(公告)日：2005-01-05

申请号：NO20044923

申请日：2004-11-11

Applicant: INTERDIGITAL TECH CORP

Inventor： HEPLER EDWARD L ,  CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  STARSINIC MICHAEL F ,  LEVI ALAN M ,  BASS DAVID S ,  DESAI BINISH

IPC: H04B1/40 ,  H04B1/707 ,  H04J1/00 ,  H04B7/26 ,  H04J3/00 ,  H04J4/00 ,  H04L1/00 ,  H04L1/08 ,  H04L12/56 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00 ,  H04W88/02 ,  G06F13/00

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

公开(公告)号：NO20034603A

公开(公告)日：2003-12-08

申请号：NO20034603

申请日：2003-10-14

Applicant: INTERDIGITAL TECH CORP

Inventor： CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  MORABITO JOSEPH T

IPC: H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H04B1/69 ,  H04B7/155 ,  H04B7/208 ,  H04B7/212 ,  H04B7/216 ,  H04B7/26 ,  H04J3/00 ,  H04J3/02 ,  H04L1/00 ,  H04Q11/00 ,  H04W88/02 ,  H04W88/08

CPC classification number: H04L1/0059 ,  H03M13/09 ,  H03M13/23 ,  H03M13/271 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6362 ,  H03M13/6513 ,  H04L1/0045 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071