公开(公告)号：DE69421266D1

公开(公告)日：1999-11-25

申请号：DE69421266

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C7/00 ,  G11C16/06

Abstract: The circuit (1) comprises a section (2) generating a pulse signal (ATD) for asynchronously enabling the read phases; a section (4) generating precharge (PC) and detecting (DET) signals of adjustable duration, for controlling data reading from the memory (104) and data supply to the output buffers (106); a section (5) generating a noise suppressing signal (N) for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal (SP) in an out-like circuit (33); a section (6) generating a loading signal (L), the duration of which may be equal to that of the noise suppressing signal (N) or extended by an extension circuit (51) in the event the array presents slower elements which may thus be read; and a section (7) generating a circuit reset signal (END).

公开(公告)号：DE69419723D1

公开(公告)日：1999-09-02

申请号：DE69419723

申请日：1994-02-18

Applicant: ST MICROELECTRONICS SRL

Inventor： PASCUCCI LUIGI ,  GOLLA CARLA MARIA ,  MACCARRONE MARCO ,  OLIVO MARCO

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

公开(公告)号：DE69411532T2

公开(公告)日：1999-03-04

申请号：DE69411532

申请日：1994-02-17

Applicant: ST MICROELECTRONICS SRL

Inventor： GOLLA CARLA MARIA ,  MACCARRONE MARCO

IPC: G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: A method for programming non-volatile row redundancy memory registers (RR1-RR4) each one associated to a respective pair of redundancy row and each one programmable to store in two subsets (1,2;1,2') of a set of memory cells (MC0-MC9) a pair of addresses of a respective pair of adjacent defective rows; each memory register is supplied with row address signals (R0-R9) and with a respective selection signal (C0-C3) belonging to a set of column address signals (CABUS); the method provides for: applying to the row address signals (R0-R9) the address of a first defective row of the pair of adjacent defective rows; activating one of the selection signals (C0-C3) for selecting the memory register which is to be programmed; applying to a further column address signal (C4) a first logic level to select for programming, in the selected memory register, a first subset (1,2) of memory cells (MC0-MC9); enabling the programming of the address of the first defective row of the pair of adjacent defective rows into the first subset (1,2) of memory cells; applying to at least a subset (R0-R3) of the row address signals (R0-R9) the address of the second defective row of the pair; applying to the further column address signal (C4) a second, opposite logic level to select for programming, in the selected memory register (RR1-RR4), at least a group (2') of memory cells (MC0-MC3) of the second subset (1,2') of the two subsets (1,2;1,2') of memory cells; enabling the programming of the address of the second defective row of the pair of adjacent defective rows into the second subset (1,2') of memory cells.