公开(公告)号：IT1221261B

公开(公告)日：1990-06-27

申请号：IT8364588

申请日：1988-06-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： OLIVO MARCO ,  PASCUCCI LUIGI ,  VILLA CORRADO

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  H01L

Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

公开(公告)号：DE69519090D1

公开(公告)日：2000-11-16

申请号：DE69519090

申请日：1995-07-28

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI

IPC: G05F3/24 ,  H02M3/07 ,  G05F1/00

Abstract: A charge pump circuit (100) comprising a plurality of voltage boost stages (20i) that are mutually parallel-connected between a supply line (21) and an output line (22), wherein each one of the stages comprises first (25i) and second (28i) charge storage means in which, respectively, a first terminal is connected to a charge and discharge node (31i, 29i) and a second terminal is connected to a boost node (27i, 27i+1) to switch between a first charge step and a second step for transferring the charge to the output line (22); an inverter (23i), in which an input node is connected to the boost node (27i) related to the first charge storage means (25i) and an output node is connected to the boost node (27i+1) related to the second charge storage means (28i); a first charge transfer diode (30i), which is connected between the charge and discharge node (31i) related to the first charge storage means (25i) and the output line (22); a second charge transfer diode (32i), which is connected between the charge and discharge node (29i) related to the second charge storage means (28i) and the output line (22); the circuit having the particularity that each one of the stages (20i) comprises an additional diode (35i) that is connected between the charge and discharge node (31i) related to the first charge storage means (25i) and the output line (22), the additional diode discharging the first charge storage means when the potential of the output line is lower than the potential, minus the threshold of the additional diode, of the charge and discharge node related to the first charge storage means.

公开(公告)号：DE69412234T2

公开(公告)日：1999-06-17

申请号：DE69412234

申请日：1994-03-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  CARRERA MARCELLO ,  DEFENDI MARCO

IPC: G11C17/00 ,  G11C5/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G06F11/20

Abstract: A Redundancy circuitry layout for a semiconductor memory device comprises an array (MAR) of programmable non-volatile memory elements (TF0,TF1) for storing the addresses of defective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines; the redundancy circuitry layout is divided in identical layout strips (LS1-LS4) which are perpendicular to the array (MAR) of memory elements (TF0,TF1) and which comprise each a first and a second strip sides located at opposite sides of the array (MAR) of memory elements (TF0,TF1), the first strip side containing at least one programmable non-volatile memory register (CRRA,CRRB) of a first plurality for the selection of redundancy bit lines and being crossed by a column address signal bus (CABUS) running parallel to the array (MAR of memory elements (TF0,TF1), the second strip side containing one programmable non-volatile memory register (RRR) of a second plurality for the selection of redundancy word lines and being crossed by a row address signal bus (RABUS) running parallel to the array (MAR) of memory elements (TF0,TF1).

公开(公告)号：DE69321245T2

公开(公告)日：1999-04-29

申请号：DE69321245

申请日：1993-12-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  PADOAN SILVIA ,  MACCARRONE MARCO

IPC: G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G06F11/20

Abstract: An integrated programming circuitry for an electrically programmable semiconductor memory device comprises a plurality of programming load circuits (PLOAD0-PLOAD15), each one associated to a respective memory matrix portion (OD0-OD15) or group of columns (BL), and a plurality of programming load control circuits (CNT0-CNT15), each one controlling the activation of one respective programming load circuit (PLOAD0-PLOAD15) according to the logic state of a respective data line (D0-D15) carrying a datum to be programmed; the memory device comprises a group (RB) of redundancy bit lines (RBL) and an associated redundancy programming load circuit (PLOADR); each programming load control circuit (CNT0-CNT15) comprises decoding means (7) supplied with signals (OC0-OC3,OC0N-OC3N) which, when a defective column address (COLADD) is supplied to the memory device during programming, are generated from a matrix portion identifying code (OC0'-OC3') stored in a non-volatile register (RR) wherein the defective column address (COLADD) is stored, and switch means (SW,6) responsive to a decoded signal (ROUT) at the output of said decoding means (7) to enable the activation of the redundancy programming load circuit (PLOADR) according to the logic state of the data signal line (D0-D15) and to cause the inhibition of the activation of the respective programming load circuit (PLOAD0-PLOAD15).

公开(公告)号：IT1289864B1

公开(公告)日：1998-10-19

申请号：ITMI970010

申请日：1997-01-08

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI

IPC: G11C20060101

公开(公告)号：IT1286037B1

公开(公告)日：1998-07-07

申请号：ITMI962210

申请日：1996-10-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI

IPC: H03K3/356 ,  H03K17/693

公开(公告)号：ITMI962762A1

公开(公告)日：1998-06-30

申请号：ITMI962762

申请日：1996-12-31

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI

IPC: H01L20060101

公开(公告)号：DE69220632D1

公开(公告)日：1997-08-07

申请号：DE69220632

申请日：1992-08-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22

Abstract: A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.

公开(公告)号：DE69115952T2

公开(公告)日：1996-09-19

申请号：DE69115952

申请日：1991-02-07

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C11/419 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18

Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCCmax. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

公开(公告)号：IT1246241B

公开(公告)日：1994-11-17

申请号：IT8360790

申请日：1990-02-23

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

IPC: G11C16/06 ,  G11C11/419 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18 ,  G11C

Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCCmax. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.