公开(公告)号：US09746832B1

公开(公告)日：2017-08-29

申请号：US15432578

申请日：2017-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chih-Wei Yao

IPC: H03M1/12 ,  G04F10/00 ,  H03M7/30 ,  H03M1/38 ,  H03M1/10 ,  H03M1/00

CPC classification number: G04F10/005 ,  H03M1/00 ,  H03M1/12 ,  H03M1/145 ,  H03M1/38 ,  H03M1/50 ,  H03M7/30 ,  H03M2201/4233

Abstract: An apparatus and a method. The apparatus includes a delay processor, a coarse converter and node selector connected to the delay processor and configured to select a first voltage V1 and a second voltage V2 of opposite polarities of adjacent stages of the delay processor, a fine converter connected to the coarse converter and node selector and configured to determine a zero-crossing time associated with the first voltage V1 and the second voltage V2; and an encoder connected to the coarse converter and the fine converter and configured to receive and encode the first voltage V1, the second voltage V2 and the zero-crossing time, wherein V1 is a first negative voltage before the zero-crossing time, and V2 is a first positive voltage after the zero-crossing time.

公开(公告)号：US09229433B1

公开(公告)日：2016-01-05

申请号：US14552241

申请日：2014-11-24

Applicant: PMC-SIERRA US, INC.

Inventor： Mark Hiebert ,  Derek J. W. Ho

IPC: H03M1/50 ,  G04F10/00 ,  H03M1/12 ,  H04L7/033 ,  H03M1/00

CPC classification number: G04F10/005 ,  G04F10/00 ,  G06F1/12 ,  H03L7/0805 ,  H03L7/087 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1255 ,  H03M2201/4233 ,  H04L7/0331

Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

公开(公告)号：US09225507B1

公开(公告)日：2015-12-29

申请号：US13910016

申请日：2013-06-04

Applicant: PMC-SIERRA US, INC.

Inventor： William Michael Lye ,  Dragos Cartina

IPC: H04L7/033 ,  G06F1/12 ,  H03L7/08

CPC classification number: G04F10/005 ,  G04F10/00 ,  G06F1/12 ,  H03L7/0805 ,  H03L7/087 ,  H03L7/1976 ,  H03L7/23 ,  H03L7/235 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1255 ,  H03M2201/4233 ,  H04L7/0331

Abstract: Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.

Abstract translation: 提供了一种用于使由第一射频（RF）路径中的可控LO时钟发生器产生的第一本地振荡器（LO）时钟与第二RF路径中的第二LO时钟对准的方法和装置。 该装置包括被配置为在第一和第二RF路径之间交换同步时钟的同步信道，被配置为测量第一和第二LO时钟之间的相位对准的相位检测器，以及被配置为使用 相位对准。 还提供了一个时间到数字转换器。 数字转换器的时间包括用于以第三时钟对第一和第二输入时钟进行采样的D触发器，以及被配置为同步地增加所得样本并产生表示第一和第二时钟之间的延迟的数字比例值的计数器。

公开(公告)号：US09106245B2

公开(公告)日：2015-08-11

申请号：US14401566

申请日：2013-03-25

Applicant: Robert Bosch GmbH

Inventor： Thomas Wuchert ,  Matthias Kalisch

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/18 ,  H04L7/04 ,  H04L5/00 ,  H04L25/03 ,  H04L27/26 ,  H04B1/40

CPC classification number: H03M1/0626 ,  G01D3/08 ,  H03M1/0629 ,  H03M1/1095 ,  H03M1/12 ,  H03M1/1245 ,  H03M1/183 ,  H03M2201/4233 ,  H04B1/40 ,  H04L5/0007 ,  H04L7/042 ,  H04L25/00 ,  H04L25/03038 ,  H04L27/2647

Abstract: A method for interference suppression of a sampling process includes sampling an analog signal with a sampling frequency f, and determining whether an interference amplitude is present. The method provides that if an interference amplitude is present, the sampling frequency f is increased or decreased, and the method begins again with the sampling of the analog signal with the increased or decreased sampling frequency. In addition, a device is described for carrying out the method.

Abstract translation: 一种采样过程的干扰抑制方法包括以采样频率f对模拟信号进行采样，并确定是否存在干扰幅度。 该方法提供如果存在干扰幅度，则采样频率f增加或减小，并且随着模拟信号采样频率的增加或减小，该方法再次开始。 此外，描述了用于执行该方法的设备。

公开(公告)号：US08890738B2

公开(公告)日：2014-11-18

申请号：US14110192

申请日：2012-04-04

Applicant: Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

Inventor： Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

IPC: H03M1/12 ,  G04F10/00 ,  H03M1/00 ,  H04L7/033

CPC classification number: G04F10/005 ,  G04F10/00 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M2201/4233 ,  H04L7/033

Abstract: The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

Abstract translation: 本公开提供了一种时间数字（TDC）转换器，包括：粗TDC接收起始信号和停止信号，以第一时间单位延迟第一起始信号以产生n个第一延迟起始信号（其中n为 等于或大于2的整数），测量第一时间单位中第一延迟起始信号和停止信号之间的时间差，以及产生通过以时间单位延迟第一延迟开始信号而获得的第二延迟起始信号 比第一时间单位短; 以及精细TDC，接收并延迟从粗TDC产生的第二延迟开始信号并接收停止信号，并且以第二时间单位测量第二延迟开始信号和停止信号之间的时间差。

公开(公告)号：US08884804B1

公开(公告)日：2014-11-11

申请号：US14089222

申请日：2013-11-25

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Siva Charan Nimmagadda ,  Baanurathan Sadasivam ,  Richard W. Swanson ,  Yohan Frans

IPC: H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H03M1/00

CPC classification number: G04F10/005 ,  H03L7/00 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0895 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233

Abstract: An apparatus relating generally to time-to-digital conversion is disclosed. In this apparatus, a time-to-digital converter is coupled to a period sensor. The period sensor includes a pulse generator to generate a pulse. An integrator of the period sensor is coupled to receive the pulse to generate an analog voltage signal responsive to the pulse. The time-to-digital converter includes an analog-to-digital converter coupled to provide a digital signal associated with the analog voltage signal.

Abstract translation: 公开了一种与时间 - 数字转换相关的装置。 在该装置中，时间 - 数字转换器耦合到周期传感器。 周期传感器包括产生脉冲的脉冲发生器。 耦合周期传感器的积分器以接收脉冲以产生响应脉冲的模拟电压信号。 时间 - 数字转换器包括耦合以提供与模拟电压信号相关联的数字信号的模拟 - 数字转换器。

公开(公告)号：US20140292552A1

公开(公告)日：2014-10-02

申请号：US14110192

申请日：2012-04-04

Applicant: Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

Inventor： Tae Wook Kim ,  Yeomyung Kim ,  Gunhee Han

IPC: G04F10/00

CPC classification number: G04F10/005 ,  G04F10/00 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M2201/4233 ,  H04L7/033

Abstract: The present disclosure provides a time-to-digital (TDC) converter, comprising: a coarse TDC receiving a start signal and a stop signal, delaying the first start signal in a first time unit to generate n first delayed start signals (where n is an integer equal to or larger than 2), measuring a time difference between the first delayed start signal and the stop signal in the first time unit, and generating second delayed start signals that are obtained by delaying the first delayed start signals in a time unit shorter than the first time unit; and a fine TDC receiving and delaying the second delayed start signal generated from the coarse TDC and receiving the stop signal, and measuring a time difference between the second delayed start signal and the stop signal in a second time unit.

Abstract translation: 本公开提供了一种时间数字（TDC）转换器，包括：粗TDC接收起始信号和停止信号，以第一时间单位延迟第一起始信号以产生n个第一延迟起始信号（其中n为 等于或大于2的整数），测量第一时间单位中第一延迟起始信号和停止信号之间的时间差，以及产生通过以时间单位延迟第一延迟开始信号而获得的第二延迟起始信号 比第一时间单位短; 以及精细TDC，接收并延迟从粗TDC产生的第二延迟开始信号并接收停止信号，并且以第二时间单位测量第二延迟开始信号和停止信号之间的时间差。

公开(公告)号：US20130300593A1

公开(公告)日：2013-11-14

申请号：US13941598

申请日：2013-07-15

Applicant: MediaTek Inc.

Inventor： Yun-Shiang SHU

IPC: H03M1/50

CPC classification number: H03M1/50 ,  H03M1/00 ,  H03M1/12 ,  H03M1/206 ,  H03M1/365 ,  H03M2201/4233

Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

Abstract translation: 提供比较电路并包括第一和第二比较器和第一时间 - 数字比较器。 具有第一偏移电压的第一比较器接收输入信号并产生第一比较信号和第一反比较信号。 第二比较器接收输入信号并产生第二比较信号和第二反比较信号。 第一偏移电压大于第二偏移电压。 第一时间数字比较器接收第一比较信号和第二反比较信号，并根据第一比较信号和第二反比较信号产生第一和第二确定信号。 第一和第二确定信号指示输入信号的电压是否大于第一中间电压。 第一中间电压等于第一偏移电压和第二偏移电压之和的一半。

公开(公告)号：US20120268105A1

公开(公告)日：2012-10-25

申请号：US13091928

申请日：2011-04-21

Applicant: Gregory J. MANN ,  Gin-Chung WANG

Inventor： Gregory J. MANN ,  Gin-Chung WANG

IPC: G01R19/22

CPC classification number: G01T1/17 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233

Abstract: A method and electronic device for outputting time values and energy of an analog input signal by dynamically determining a plurality of threshold values, comparing, using a plurality of comparator circuits, the plurality of threshold values against the analog input signal, outputting, using at least one time to digital conversion circuit connected to each of the plurality of comparator circuits, a plurality of time values, each time value output when the analog input signal meets or exceeds a threshold value of the threshold values, filtering the analog input signal, performing, using an analog-to-digital conversion circuit, analog-to-digital conversion of the filtered analog input signal to generate a digital signal, and calculating, in response to receiving a trigger signal, an energy of the digital signal.

Abstract translation: 一种用于通过动态地确定多个阈值来输出模拟输入信号的时间值和能量的方法和电子装置，使用多个比较器电路比较多个阈值与模拟输入信号的比较，至少使用 连接到多个比较器电路中的每一个的一次数字转换电路，多个时间值，当模拟输入信号达到或超过阈值的阈值时输出每个时间值，对模拟输入信号进行滤波， 使用模数转换电路，对经过滤波的模拟输入信号进行模数转换以产生数字信号，以及响应于接收到触发信号计算数字信号的能量。

公开(公告)号：US4862170A

公开(公告)日：1989-08-29

申请号：US171812

申请日：1988-03-22

Applicant: Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

Inventor： Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

IPC: G11B20/10 ,  H03M1/00 ,  H03M1/66

CPC classification number: H03M1/00 ,  H03M2201/03 ,  H03M2201/196 ,  H03M2201/30 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/526 ,  H03M2201/6121 ,  H03M2201/721

Abstract: A digital analog converter which is especially suitable for use in converting a digital audio signal into an analog audio signal includes a unit pulse response signal generator for successively generating unit pulse response signals at a predetermined time interval, a digital data generator for generating digital data at the predetermined time interval, a multiplier for multiplying a unit pulse response signal generated at a certain time by a predetermined item of the digital data, and a mixer for producing an analog signal output by combining the unit pulse response signals that have been multiplied by the digital data.

Abstract translation: 特别适用于将数字音频信号转换为模拟音频信号的数字模拟转换器包括用于以预定的时间间隔连续产生单位脉冲响应信号的单位脉冲响应信号发生器，用于产生数字数据的数字数据发生器 所述预定时间间隔，用于将在某一时间产生的单位脉冲响应信号乘以数字数据的预定项目的乘法器和用于产生模拟信号的混频器，所述混频器通过将已经乘以所述单位脉冲响应信号 数字数据。