-
公开(公告)号：JP2003163278A
公开(公告)日：2003-06-06
申请号：JP2002307000
申请日：2002-10-22
Applicant: ST MICROELECTRONICS SA
Inventor： MALHERBE ALEXANDRE , BLISSON FABRICE
IPC: H01L27/04 , H01L21/822 , H01L27/02 , H01L27/06
Abstract: PROBLEM TO BE SOLVED: To provide a protection circuit occupying a small area in an integrated circuit for protecting the integrated circuit against electrostatic discharges and overvoltages. SOLUTION: The integrated circuit comprises at least one element of an electronic protection circuit having at least one switch for short-circuiting supply conductors formed on a rail, wherein the switch is integrated in the rail under the conductors. COPYRIGHT: (C)2003,JPO
-
公开(公告)号：JP2003124844A
公开(公告)日：2003-04-25
申请号：JP2002269458
申请日：2002-09-17
Applicant: ST MICROELECTRONICS NV , ST MICROELECTRONICS SA
Inventor： CATTANEO CHIARA , HELAL DIDIER , ARNAUD THIERRY , LEBOWSKY FRITZ , CATTENOZ REGIS
Abstract: PROBLEM TO BE SOLVED: To decode an incident pulse signal of the ultra wideband type through digital processing. SOLUTION: The incident pulse signal of the ultra wideband type conveys digital information encoded by using pulses in a known theoretical shape. A decoding device is equipped with an input means which receives the incident signal and sends a base signal out, a preprocessing means which is so adapted as to receive the base signal and sends out an intermediate signal representing the code of the base signal with respect to a reference, a means which samples an intermediate ISN signal and sends a digital signal out, a synchronizing means, a decoding means, and a digital processing means which is so adapted as to correlate the digital signal with a reference correlation signal corresponding to a theoretical base signal arising from the reception of the theoretical pulses having the known theoretical shape.
-
公开(公告)号：JP2003084859A
公开(公告)日：2003-03-19
申请号：JP2002161409
申请日：2002-06-03
Applicant: St Microelectronics Sa , エステーミクロエレクトロニクス ソシエテ アノニム
Inventor： NICOLAI JEAN
IPC: G06F1/04 , G06F1/08 , H03K3/0231
CPC classification number: G06F1/08 , H03K3/0231
Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit equipped with an internal clock having no such defect that an oscillating frequency fluctuates in dependence on a power supply voltage of a circuit or variation in manufacturing. SOLUTION: In this integrated circuit, a processor (CPU) and an oscillator (OSC) are integrated in the same substrate, and a data resistor (R1) which can be loaded by the processor is provided. The oscillator functions as a clock for the processor, and is a relaxation oscillator equipped with a capacitor (C) and a current source for charge and discharge of the capacitor. The data resistor controls frequency adjustment of the relaxation oscillator by controlling the value of the charge and discharge current of the capacitor, and is loaded by the processor from an electrically programmable and nonvolatile memory (M1) provided in the same substrate of the integrated circuit while storing frequency correction data.
Abstract translation: 要解决的问题：提供一种配备有内部时钟的集成电路，该内部时钟没有这样的缺陷，即振荡频率根据电路的电源电压或制造变化而波动。 解决方案：在该集成电路中，处理器（CPU）和振荡器（OSC）集成在同一衬底中，并且提供可由处理器加载的数据电阻器（R1）。 振荡器用作处理器的时钟，并且是配备有电容器（C）的弛豫振荡器和用于电容器的充电和放电的电流源。 数据电阻器通过控制电容器的充电和放电电流的值来控制张弛振荡器的频率调节，并且由处理器从设置在集成电路的同一衬底中的电可编程和非易失性存储器（M1）加载， 存储频率校正数据。
-
74.发明专利
公开(公告)号：JP2003060095A
公开(公告)日：2003-02-28
申请号：JP2002178046
申请日：2002-06-19
Applicant: St Microelectronics Sa , エスティマイクロエレクトロニクス エスエー
Inventor： SKOTNICKI THOMAS , VILLARET ALEXANDRE
IPC: H01L27/10 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC classification number: H01L29/42336 , H01L29/788
Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor memory device having hybrid performance. SOLUTION: The integrated semiconductor memory device is provided with an integrated memory structure CH2 provided with a semiconductor layer surrounded by an isolation layer, lying between the source region S and the drain region D of a transistor and inserted between the channel region of the transistor and its control gate. The semiconductor layer included two potential well zones Z1 and Z3 separated by a potential barrier zone Z2 lying beneath the control gate of the transistor. Write means Vg and Vds bias the memory structure so as to confine charge carriers selectively in one or other of the two potential well zones, and read means Vg and Vd bias the memory structure so as to detect, for example by measuring the drain current of the transistor, the presence of charge carriers in one or other of the potential wells.
Abstract translation: 要解决的问题：提供具有混合性能的集成半导体存储器件。 解决方案：集成半导体存储器件设置有集成存储器结构CH2，其设置有由隔离层围绕的半导体层，该隔离层位于晶体管的源极区域S和漏极区域D之间，并且插入在晶体管的沟道区域和晶体管的沟道区域之间 其控制门。 半导体层包括由位于晶体管的控制栅极下方的势垒区Z2分开的两个势阱区Z1和Z3。 写装置Vg和Vds偏置存储器结构，以便将电荷载流子选择性地限制在两个势阱区域中的一个或另一个中，并且读装置Vg和Vd偏置存储器结构，以便例如通过测量漏极电流 晶体管，在一个或另一个势阱中存在电荷载体。
-
公开(公告)号：JP2002334589A
公开(公告)日：2002-11-22
申请号：JP2002026723
申请日：2002-02-04
Applicant: ST MICROELECTRONICS SA
Inventor： FOURNEL RICHARD , AITOUARAB LEILA SEDJAI
Abstract: PROBLEM TO BE SOLVED: To prevent a read error caused by variation of a property of a reference memory cell. SOLUTION: This method is a method for refreshing a reference memory cell (Cref) in a non-volatile memory. This method has a step in which the reference cell (Cref) and a test cell (Cveri) are simultaneously selected during read, read signals are compared when a signal read by the reference cell is smaller than a signal read by the test cell, and refresh signals (Sr1, Sr2, Sr3) are outputted to the reference cell (Cref). This method is applied to an electronic memory of a non-volatile type.
-
Patent Agency Ranking
公开(公告)号：JP2002270509A
公开(公告)日：2002-09-20
申请号：JP2001394184
申请日：2001-12-26
Applicant: ST MICROELECTRONICS SA
Inventor： MENUT OLIVIER , GRIS YVON
IPC: H01L21/76 , H01L21/20 , H01L21/205 , H01L21/329 , H01L21/762 , H01L21/822 , H01L27/04 , H01L29/861
Abstract: PROBLEM TO BE SOLVED: To manufacture a single crystal substrate allowing a silicon epitaxial layer having no crystal defect to be formed thereafter. SOLUTION: The manufacturing method comprises a step of forming an initial single crystal substrate having at least one crystal lattice discontinuity locally on the surface, recessing the discontinuous spot of the initial substrate, making a crystal lattice around the recess amorphous, depositing a layer of an amorphous material having the same chemical composition as the initial substrate on an obtained structure, and thermally annealing the obtained structure to re-crystallize the amorphous portions so as to continue the single crystal lattice of the initial substrate.
-
公开(公告)号：JP2002009661A
公开(公告)日：2002-01-11
申请号：JP2001140158
申请日：2001-05-10
Applicant: ST MICROELECTRONICS SA
Inventor： WUIDART LUC
Abstract: PROBLEM TO BE SOLVED: To provide a method for reducing a time required to initialize and set up communication between a read/write terminal for electromagnetic transponders and the one transponder entering a field of the terminal or more, that is, to provide a method for decreasing consecutive times required for the read/write terminal, in order to decide and identify all the transponders present in the terminal field at a specific time. SOLUTION: This invention provides the method for establishing communication between devices that include the terminal, which is adapted so as to cooperate with the transponder, when at least the one transponder enters the terminal field and uses an oscillation circuit to generate a high-frequency electromagnetic field, a circuit that adjusts a signal phase of the oscillation circuit with respect to a reference value, and a circuit that evaluates a minimum number of the transponders present in the field, on the basis of the measurement of a current of the oscillation circuit.
-
公开(公告)号：JP2001266102A
公开(公告)日：2001-09-28
申请号：JP2001026126
申请日：2001-02-01
Applicant: ST MICROELECTRONICS SA
Inventor： ROBERTS ANDREW J , SUBBIOTTO FREDERIC
Abstract: PROBLEM TO BE SOLVED: To provide a demodulator for non-contact chip card, which is not affected by the level of a received signal. SOLUTION: A non-contact chip card where binary data is transmitted by a radio frequency includes a demodulator for binary data. The demodulator includes a circuit for detecting a transmitted signal, a rectifying circuit, a band pass filter, a comparator stage and a memory circuit. The band pass filter gives a low frequency signal used as a reference for two comparators and a high frequency signal supplied for comparison with the reference which changes with the low frequency signal. Consequently, demodulation is not affected by the average level of the received signal.
-
公开(公告)号：JP2001237825A
公开(公告)日：2001-08-31
申请号：JP2000366035
申请日：2000-11-30
Applicant: ST MICROELECTRONICS SA
Inventor： POMET ALAIN , PLESSIER BERNARD , SOURGEN LAURENT
Abstract: PROBLEM TO BE SOLVED: To prevent a data element moving via a bus from being identified or to hardly make the data element identified. SOLUTION: In the electronic component provided with a 2-way bus DATA- BUS through which the data element is moved at a speed of a clock signal PHI between peripheral devices P1, P2, P3 and a central processing unit CPU, each of the central processing unit CPU and at least one peripheral device P1 is provided with a data encryption/decoding cell Kcell employing respectively the same private key KEY, a random signal Kin synchronously with the clock signal PHI is uniquely outputted at each clock cycle of each cell as the current value of the private key and applied to the respective cells through a unidirectional transmission line.
-
公开(公告)号：JP2001230257A
公开(公告)日：2001-08-24
申请号：JP2001031574
申请日：2001-02-07
Applicant: ST MICROELECTRONICS SA , KONINKL PHILIPS ELECTRONICS NV
Inventor： KORDIC SRDJAN , TORRES JOAQUIM , MOTTE PASCALE , DESCOUTS BRIGITTE
IPC: H01L23/52 , H01L21/3205 , H01L23/522 , H01L23/532
Abstract: PROBLEM TO BE SOLVED: To avoid increase of resistivity of a metallic track caused by silicon diffusion to copper. SOLUTION: This process comprises a step for generating at least one metallic track 7 in an inside of a track insulation material 1 at a predetermined metallization level. The generation step of the metallization track 7 comprises an etching step of the track insulation material 1 forming a clearance 4 in the position of the track, a step for depositing a conduction barrier layer 5 in the clearance, a step for filling the clearance with copper, and a step for depositing a silicon nitride layer 8 on the predetermined metallization level. Titanium is deposited in at least a barrier layer between a deposition step of a barrier layer and a filling step of copper. The titanium changes to TiSi2 (60) during silicon diffusion from the silicon nitride layer 8.
-
-
-
-
-
-
-
-
-
Search Results
4906
records
(took 0.03 seconds)
