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公开(公告)号：KR1020110052939A
公开(公告)日：2011-05-19
申请号：KR1020090109692
申请日：2009-11-13
Applicant: 삼성전자주식회사
IPC: H01L29/786 , G02F1/1333
CPC classification number: H01L29/7869 , H01L29/78696 , H01L27/1225 , H01L29/26
Abstract: PURPOSE: A transistor, a manufacturing method thereof, and an electrode device including the same are provided to improve the reliability of a flat panel display device by including the transistor which suppresses the change of a property due to light. CONSTITUTION: A gate(G1) is formed on a substrate(SUB1). A gate insulation layer(Gl1) is formed on the substrate to cover the gate. A channel layer(C1) is formed on the gate insulation layer and is made of oxide with In and Zn and a first element. A source(S1) and a drain(D1) are connected to both sides of the channel layer.
Abstract translation: 目的：提供晶体管及其制造方法以及包括该晶体管的电极器件，以通过包括抑制由于光引起的特性变化的晶体管来提高平板显示装置的可靠性。 构成：在基板（SUB1）上形成栅极（G1）。 在基板上形成栅极绝缘层（Gl1）以覆盖栅极。 沟道层（C1）形成在栅极绝缘层上，并由In和Zn和第一元素的氧化物构成。 源极（S1）和漏极（D1）连接到沟道层的两侧。
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公开(公告)号：KR1020110050926A
公开(公告)日：2011-05-17
申请号：KR1020090107517
申请日：2009-11-09
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78696 , H01L29/7869 , H01L29/06
Abstract: PURPOSE: A transistor, a manufacturing method thereof, and an electronic device including the same are provided to prevent the change of a property due to a residual charge trap generated in a channel layer due to light by suppressing a trap site through an oxygen rich layer. CONSTITUTION: A gate insulation layer(GI1) covering a gate(G1) is formed on a substrate(SUB1). A channel layer(C1) with a multi layer is formed on the gate insulation layer. The channel layer includes a first oxide layer(R1) and a second oxide layer(P1). A source electrode(S1) and a drain electrode(D1) connected to both sides of the channel layer are formed on the gate insulation layer. A passivation layer(PS1) is formed on the gate insulation layer to cover the channel layer, the source electrode, and the drain electrode.
Abstract translation: 目的：提供一种晶体管及其制造方法以及包括该晶体管的电子器件，以防止由于通过富氧层抑制捕获部位而引起的光在通道层中产生的残留电荷陷阱而引起的特性变化 。 构成：在基板（SUB1）上形成覆盖栅极（G1）的栅极绝缘层（GI1）。 在栅极绝缘层上形成具有多层的沟道层（C1）。 沟道层包括第一氧化物层（R1）和第二氧化物层（P1）。 在栅绝缘层上形成与沟道层两侧连接的源电极（S1）和漏电极（D1）。 在栅绝缘层上形成钝化层（PS1），以覆盖沟道层，源电极和漏电极。
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公开(公告)号：KR100935936B1
公开(公告)日：2010-01-11
申请号：KR1020080047092
申请日：2008-05-21
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: G11C17/00 , H01L21/8239 , H01L23/12
Abstract: 본 발명은 적층 메모리 장치에 관한 것이다. 적층 메모리 장치에 있어서, 적층된 다수의 메모리층을 각각 포함하는 두 개 이상의 메모리부와 메모리부들 사이에 형성된 것으로, 디코더를 구비하는 적어도 하나의 능동회로부 포함하는 적층 메모리 장치를 제공한다.
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公开(公告)号：KR1020090084236A
公开(公告)日：2009-08-05
申请号：KR1020080010291
申请日：2008-01-31
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
Abstract: A memory chip array is provided to reduce the whole size by arranging a circuit related to column operation such as a sense amplifier and a column decoder. A memory chip array comprises a plurality of cell arrays(20) and a row decoder. The row decoder comprises a low select(22) and a pre-decoder(21), and the low select is formed in one-side of each cell array. A plurality of cell arrays are connected to pre-decoder in common, and the sense amplifier and the column decoder(23) are formed in the lower-part of each cell array.
Abstract translation: 提供存储器芯片阵列以通过布置与诸如读出放大器和列解码器的列操作相关的电路来减小整体尺寸。 存储芯片阵列包括多个单元阵列（20）和行解码器。 行解码器包括低选择（22）和预解码器（21），并且低选择形成在每个单元阵列的一侧。 多个单元阵列共同连接到预解码器，并且读出放大器和列解码器（23）形成在每个单元阵列的下部。
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公开(公告)号：KR1020090037712A
公开(公告)日：2009-04-16
申请号：KR1020070103192
申请日：2007-10-12
Applicant: 삼성전자주식회사
CPC classification number: G06F21/575
Abstract: An electronic device for security boot up and a method for computation hash vale and boot-up operation thereof are provided to decrease a production cost and a chip size by reducing hash code stored in the E-fuse memory. A flash memory(120) stores the boot code and public key. A processor(111) enforces the boot code. An E-fuse memory(113) stores the first hash value. A block encrypting unit(115) calculates the second Hash value of the public key with the block cryptographic algorithm. The block cryptographic algorithm uses a part of the public key as the first input value. The first hash value stored in the second memory is the value hashing the public key with the block cryptographic algorithm. The boot code comprises command codes. The command code determines whether a processor calculates the Hash value of the public key stored in the nonvolatile memory, reads the Hash value stored in E-fuse memory, and compares the calculated Hash value with the Hash value read from the E-fuse memory. When the calculated Hash value matches with the Hash value read from the E-fuse, the command code enforces the processor to execute a boot code.
Abstract translation: 提供一种用于安全启动的电子设备和用于计算散列值和启动操作的方法，以通过减少存储在电熔丝存储器中的散列码来降低生产成本和芯片尺寸。 闪存（120）存储引导代码和公钥。 处理器（111）强制引导代码。 电子熔丝存储器（113）存储第一散列值。 块加密单元（115）利用块加密算法计算公开密钥的第二哈希值。 块加密算法使用公钥的一部分作为第一输入值。 存储在第二存储器中的第一个哈希值是使用块加密算法对公钥进行散列的值。 引导代码包括命令代码。 命令代码确定处理器是否计算存储在非易失性存储器中的公用密钥的哈希值，读取存储在电熔丝存储器中的哈希值，并将计算的哈希值与从电子熔丝存储器读取的哈希值进行比较。 当计算的哈希值与从电子熔丝读取的哈希值匹配时，命令代码强制处理器执行引导代码。
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Patent Agency Ranking
公开(公告)号：KR100888614B1
公开(公告)日：2009-03-17
申请号：KR1020050014652
申请日：2005-02-22
Applicant: 삼성전자주식회사
IPC: H04L9/06
Abstract: 본 발명에 따른 RC4 알고리즘을 하드웨어로 구현한 보안 알고리즘 회로 및 데이터 암호화 방법에 관한 것이다. 본 발명에 따른 보안 알고리즘 회로는 S박스, 읽기 제어 로직, 레지스터, 그리고 쓰기 제어 로직을 포함한다. 상기 S박스는 제 1 및 제 2 포트를 가지며, 하나의 클록 신호에 응답하여 제 1 포트를 통해 데이터를 출력하고, 동시에 제 2 포트를 통해 데이터를 입력받는다. 상기 읽기 제어 로직은 상기 제 1 포트에 연결되며, 상기 S박스의 읽기 동작을 제어한다. 상기 레지스터는 상기 읽기 제어 로직에서 출력된 어드레스 및 상기 S박스에서 출력된 데이터를 저장한다. 상기 쓰기 제어 로직은 상기 레지스터에 저장된 어드레스 및 데이터를 입력받고, 상기 S박스의 쓰기 동작을 제어한다. 본 발명에 따른 보안 알고리즘 회로는 읽기 제어 로직과 쓰기 제어 로직을 따로 구비하고 있기 때문에 보안 알고리즘의 설계가 용이하며, 듀얼 포트 에스램을 사용하여 파이프 라인 방식으로 동작하기 때문에 종래에 비해 클록수를 줄일 수 있다.
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公开(公告)号：KR1020090022186A
公开(公告)日：2009-03-04
申请号：KR1020070087307
申请日：2007-08-29
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02581 , H01L29/78696
Abstract: An oxide thin film transistor and a manufacturing method thereof are provided to improve electrical characteristic by forming a capping layer with high work function in a channel region. A channel(14) and a capping layer(15) with a work function higher than the channel are consecutively formed in the position corresponding to a gate(12). A gate insulator(13) is formed between the gate and the channel. A source(16a) and a drain(16b) are formed while contacting two parts of the capping layer. A passivation layer is formed by coating the insulating material on the capping layer. The channel is made of the In-Zn oxide coated with Ni.
Abstract translation: 提供一种氧化物薄膜晶体管及其制造方法，通过在沟道区域形成具有高功函数的覆盖层来提高电气特性。 具有比通道高的功函数的通道（14）和盖层（15）在对应于门（12）的位置处连续地形成。 栅极绝缘体（13）形成在栅极和沟道之间。 形成源极（16a）和漏极（16b），同时接触覆盖层的两个部分。 通过在绝缘层上涂覆绝缘材料形成钝化层。 该通道由镀Ni的In-Zn氧化物制成。
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公开(公告)号：KR1020080112877A
公开(公告)日：2008-12-26
申请号：KR1020070061875
申请日：2007-06-22
Applicant: 삼성전자주식회사
IPC: H01L29/786 , H01L21/302
CPC classification number: C09K13/06 , H01L21/467 , H01L29/7869
Abstract: An etching solution of a Zn oxide and a Zn oxide thin film transistor are provided to remove damage area formed in a channel in a source and drain forming process as a channel surface is partly removed and a recessed portion is formed. A Zn oxide thin film transistor comprises a gate(32), a channel(34), a gate insulator, a source(35a), a drain(35b), and a recessed portion(R). The channel is formed of a Zn oxide in a location corresponding to the gate. The gate insulator is formed between the gate and channel. The source and drain are formed with contacting two part of the channel. The recessed portion is formed in the channel between the drain and source.
Abstract translation: 提供Zn氧化物和Zn氧化物薄膜晶体管的蚀刻溶液以去除在源极和漏极形成过程中形成的沟道中的损伤区域，因为部分地去除沟道表面并形成凹陷部分。 Zn氧化物薄膜晶体管包括栅极（32），沟道（34），栅极绝缘体，源极（35a），漏极（35b）和凹陷部分（R）。 沟道由与栅极对应的位置的Zn氧化物形成。 栅极绝缘体形成在栅极和沟道之间。 源极和漏极形成为接触通道的两部分。 凹陷部分形成在漏极和源极之间的沟道中。
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