公开(公告)号：KR1020150043933A

公开(公告)日：2015-04-23

申请号：KR1020130122956

申请日：2013-10-15

Applicant: 삼성전자주식회사

Inventor： 박재화 ,  문광진 ,  강성희 ,  김태성 ,  박병률 ,  방석철 ,  진정기

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/00

Abstract: 집적회로소자는기판상의제1 영역에서서로다른레벨에형성된복수의제1 배선층과, 복수의제1 배선층을연결하는복수의제1 콘택플러그를포함하는제1 다층배선구조와, 기판상의제2 영역에서복수의제1 배선층중 적어도하나의제1 배선층과동일레벨에형성되는제1 패드층과, 복수의제1 콘택플러그중 적어도하나의제1 콘택플러그와동일레벨에형성되고제1 패드층에접하는제2 패드층을포함하는 TSV 랜딩패드와, TSV 랜딩패드위에형성된제2 다층배선구조와, 기판을관통하여 TSV 랜딩패드를통해제2 다층배선구조에연결되는 TSV 구조를포함한다.

Abstract translation: 集成电路装置包括：在基板上的第一区域上以不同层次形成的多个第一布线层; 第一多层布线结构，具有连接到所述多个第一布线层的多个第一接触插塞; 与所述基板的第二区域上的所述多个第一布线层中的一个以上的第一布线层相同水平的第一焊盘层; TSV着陆板，其具有与所述第一焊盘层上的所述多个第一接触插塞中的一个或多个第一接触插塞相同的水平层形成的第二焊盘层; 形成在TSV着陆板上的第二多层布线结构; 以及穿透基板并通过TSV着陆板连接到第二多层布线结构的TSV结构。

公开(公告)号：KR1020140073705A

公开(公告)日：2014-06-17

申请号：KR1020120141235

申请日：2012-12-06

Applicant: 삼성전자주식회사

Inventor： 박재화 ,  손웅희 ,  강만석 ,  박희숙

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66621 ,  H01L27/10876 ,  H01L29/4236

Abstract: Provided is a semiconductor device. The semiconductor device includes a gate trench crossing an active region of a semiconductor substrate. A gate structure filled in the gate trench is disposed. Source and drain regions are disposed within the active region at both sides of the gate structure. The gate structure includes a gate electrode and an insulating capping pattern which are staked in order and a gate dielectric between the gate electrode and the active region. The gate electrode is disposed in a lower level that that of the upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first portion with a first width and a second portion with a second width larger than the first width. The barrier conductive pattern is disposed between the first portion of the gate conductive pattern and the gate dielectric.

Abstract translation: 提供一种半导体器件。 半导体器件包括与半导体衬底的有源区交叉的栅极沟槽。 设置填充在栅极沟槽中的栅极结构。 源极和漏极区域设置在栅极结构两侧的有源区域内。 栅极结构包括栅电极和绝缘覆盖图案，其在栅极电极和有源区域之间依次被放样并形成栅极电介质。 栅电极设置在有源区的上表面的较低电平，并且包括阻挡导电图案和栅极导电图案。 栅极导电图案包括具有第一宽度的第一部分和具有大于第一宽度的第二宽度的第二部分。 阻挡导电图案设置在栅极导电图案的第一部分和栅极电介质之间。

公开(公告)号：KR1020130034343A

公开(公告)日：2013-04-05

申请号：KR1020110098308

申请日：2011-09-28

Applicant: 삼성전자주식회사

Inventor： 박재화 ,  강만석 ,  박희숙 ,  손웅희

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/76877 ,  H01L21/28562 ,  H01L21/743 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76876 ,  H01L21/76883 ,  H01L27/10891 ,  H01L21/76831

Abstract: PURPOSE: A semiconductor device including a metal-containing conductive line is provided to increase the size of a metal grain by using a thermal process for a lamination structure and to reduce the resistance of a conductive line including the metal grain. CONSTITUTION: A metal-containing barrier layer is formed on a semiconductor substrate including a conductive region(S10). A metal-containing lamination structure is formed on the metal-containing barrier layer. The metal-containing lamination structure has at least one metal layer including at least two seed layers and metal grains(S20). One part of the metal-containing lamination structure is etched to form a metal-containing line pattern consisting of the other part of the metal-containing lamination structure(S30). The metal-containing line pattern is heat-treated to increase the size of metal grains included in the metal-containing line pattern(S40). [Reference numerals] (AA) Start; (BB) End; (S10) Forming a metal-containing barrier layer on a semiconductor substrate; (S20) Forming at least two seed layers and a metal-containing lamination structure interposed between the two seed layers and including at least one metal layer and multiple metal grains on the metal-containing barrier layer; (S30) Forming a metal-containing line pattern by etching one part of the metal-containing lamination structure; (S40) Increasing the size of metal grains by heat-treating the metal-containing line pattern;

Abstract translation: 目的：提供包括含金属导电线的半导体器件，以通过使用用于层压结构的热处理来增加金属颗粒的尺寸，并且降低包括金属颗粒的导电线的电阻。 构成：在包括导电区域的半导体衬底上形成含金属阻挡层（S10）。 在含金属的阻挡层上形成含金属的层叠结构体。 含金属层压结构具有至少一个包含至少两个种子层和金属颗粒的金属层（S20）。 蚀刻含金属层压结构的一部分以形成由含金属层压结构的其它部分组成的含金属线图案（S30）。 含金属线图案被热处理以增加包含在含金属线条图案中的金属颗粒的尺寸（S40）。 （附图标记）（AA）开始; （BB）结束; （S10）在半导体衬底上形成含金属的阻挡层; （S20）在两个种子层之间形成至少两个种子层和含金属的层压结构，并且在含金属的阻挡层上包含至少一个金属层和多个金属颗粒; （S30）通过蚀刻一部分含金属层压结构体来形成含金属线图案; （S40）通过热处理含金属线图案来增加金属颗粒的尺寸;

公开(公告)号：KR1020090101592A

公开(公告)日：2009-09-29

申请号：KR1020080026819

申请日：2008-03-24

Applicant: 삼성전자주식회사

Inventor： 박재화 ,  최길현 ,  박희숙 ,  백종민

IPC: H01L21/316 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/28247 ,  H01L21/28273 ,  H01L21/31654 ,  H01L21/32105 ,  H01L29/6659 ,  H01L29/7833

Abstract: PURPOSE: A method for forming an oxide layer and a method for forming a gate using the same are provided to improve a characteristic of a silicon oxide layer by reducing a trap site in an interface between a silicon oxide layer and the silicon. CONSTITUTION: The gas with oxygen and the hydrogen are used on a layer including the silicon. An oxide layer is selectively formed on the layer including the silicon by a plasma process by adding helium to reduce the flow rate of the hydrogen below 50% of the whole flow rate. A conductive layer including a gate oxide layer, a polysilicon layer, and the metal is stacked on a substrate(200). A gate oxide layer pattern(202a), a polysilicon layer pattern, and a conductive layer pattern(206a) are formed by successively patterning the conductive layer, the polysilicon layer, and the gate oxide layer.

Abstract translation: 目的：提供一种形成氧化物层的方法和使用其形成栅极的方法，以通过减少硅氧化物层和硅之间的界面中的陷阱位置来改善氧化硅层的特性。 构成：含有氧和氢的气体用于包括硅的层。 通过加入氦气通过等离子体工艺在包含硅的层上选择性地形成氧化物层，以将氢的流量降低到全部流速的50％以下。 在衬底（200）上堆叠包括栅氧化层，多晶硅层和金属的导电层。 通过对导电层，多晶硅层和栅极氧化物层进行连续构图，形成栅极氧化物层图案（202a），多晶硅层图案和导电层图案（206a）。

公开(公告)号：KR1020090083093A

公开(公告)日：2009-08-03

申请号：KR1020080009061

申请日：2008-01-29

Applicant: 삼성전자주식회사

Inventor： 백종민 ,  정성희 ,  최길현 ,  차태호 ,  박희숙 ,  이병학 ,  박재화

IPC: H01L21/24

CPC classification number: H01L21/28061 ,  H01L29/4933

Abstract: A semiconductor device and a method for fabricating the same are provided to form a semiconductor device including a tungsten thin film of low resistivity by controlling the weight of the nickel. The semiconductor device comprises the alloy film of nickel and tungsten. Particularly, in the total weight of the alloy film of the tungsten and nickel, the weight of the nickel is the range of 0.01 weight% to 5.0 weight%. The tungsten thin film, the tungsten thin film and the nickel thin film are successively deposited and are heated for 5 minutes to 15 minutes under a temperature of 750‹C to 950‹C by the annealing process. The alloy film of the nickel and tungsten is formed by the physical vapor deposition using the sputtering target including the alloy of the nickel and tungsten. The alloy film of the nickel and tungsten comprises a part of the gate pattern, a part of the bit line pattern, and a part of a part of the contact pattern or the wiring pattern.

Abstract translation: 提供半导体器件及其制造方法，以通过控制镍的重量来形成包括具有低电阻率的钨薄膜的半导体器件。 半导体器件包括镍和钨的合金膜。 特别地，在钨和镍的合金膜的总重量中，镍的重量为0.01重量％至5.0重量％的范围。 依次沉积钨薄膜，钨薄膜和镍薄膜，并通过退火工艺在750℃至950℃的温度下加热5分钟至15分钟。 通过使用包括镍和钨的合金的溅射靶的物理气相沉积形成镍和钨的合金膜。 镍和钨的合金膜包括栅极图案的一部分，位线图案的一部分以及接触图案或布线图案的一部分的一部分。

公开(公告)号：KR1020080099900A

公开(公告)日：2008-11-14

申请号：KR1020070045773

申请日：2007-05-11

Applicant: 삼성전자주식회사

Inventor： 손웅희 ,  최길현 ,  김병희 ,  이병학 ,  박희숙 ,  박재화

IPC: H01L21/336

Abstract: The electric field concentration generated in the edge portion of the gate structure can be prevented by rounding the edge portion of the gate structure through the plasma oxidation process. The reliability of the gate dielectric layer can be improved. Provided is the gate patterning method of the semiconductor device. The gate dielectric layer(105) is formed on the semiconductor substrate. The gate structure(121) is formed on the gate dielectric layer. The plasma oxidation process(130) is progressed on the substrate having gate structure in the processing condition which is higher than 450 degree C. The gate structure includes at least one of the polysilicon layer, the metal layer, and the metal silicide layer.

Abstract translation: 可以通过等离子体氧化处理使栅极结构的边缘部分变圆来防止在栅极结构的边缘部分产生的电场浓度。 可以提高栅极电介质层的可靠性。 提供了半导体器件的栅极图案化方法。 栅电介质层（105）形成在半导体衬底上。 栅极结构（121）形成在栅极电介质层上。 等离子体氧化处理（130）在高于450℃的处理条件下在具有栅极结构的衬底上进行。栅极结构包括多晶硅层，金属层和金属硅化物层中的至少一个。

公开(公告)号：KR1020080077494A

公开(公告)日：2008-08-25

申请号：KR1020070017107

申请日：2007-02-20

Applicant: 삼성전자주식회사

Inventor： 박재화 ,  이병학 ,  손웅희 ,  최길현 ,  김병희 ,  박희숙

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L21/28176 ,  H01L21/02252 ,  H01L21/28247 ,  H01L29/4925 ,  H01L29/51

Abstract: A method for forming a semiconductor device is provided to improve reliability of gate oxide layer by recovering the damaged gate oxide layer. A method for forming semiconductor device comprises the steps of: forming a gate insulation layer(102) on a semiconductor substrate(100); forming a gate conductive layer on the gate insulation layer(104, 106); forming a gate pattern after patterning the gate conductive layer and a gate insulation layer; and including a plasma re-oxidation process using a mixed gas which is composed of oxygen gas and hydrogen gas.

Abstract translation: 提供一种用于形成半导体器件的方法，以通过恢复损坏的栅极氧化物层来提高栅极氧化物层的可靠性。 一种形成半导体器件的方法包括以下步骤：在半导体衬底（100）上形成栅极绝缘层（102）; 在栅极绝缘层（104,106）上形成栅极导电层; 在图案化栅极导电层和栅极绝缘层之后形成栅极图案; 并且包括使用由氧气和氢气组成的混合气体的等离子体再氧化工艺。

公开(公告)号：KR1020080062181A

公开(公告)日：2008-07-03

申请号：KR1020060137641

申请日：2006-12-29

Applicant: 삼성전자주식회사

Inventor： 박재화 ,  최길현 ,  김병희 ,  이병학 ,  박희숙 ,  손웅희

IPC: H01L21/3065

CPC classification number: H01L21/32139 ,  G03F7/427

Abstract: A method of fabricating a semiconductor device is provided to prevent oxidization of an exposed metal pattern even by performing an ashing process using an oxygen gas, thereby preventing metal consumption. A metal layer(102) is formed on a semiconductor substrate(100), and then a photoresist pattern(106) is formed on the metal layer. The metal layer is etched by using the photoresist pattern as an etch mask to expose a sidewall of the metal layer. The photoresist pattern formed on the metal layer is removed by using a plasma ashing process using a mixture gas containing a hydrogen gas. The metal layer comprises Ti, TiN, W, WN, Ru, Pt, An or a mixture thereof. The mixture gas comprises an oxygen gas, ozone or a mixture thereof.

Abstract translation: 提供一种制造半导体器件的方法，以防止暴露的金属图案的氧化，即使通过使用氧气进行灰化处理，从而防止金属消耗。 在半导体衬底（100）上形成金属层（102），然后在金属层上形成光刻胶图形（106）。 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻金属层以暴露金属层的侧壁。 通过使用包含氢气的混合气体的等离子体灰化处理，去除在金属层上形成的光刻胶图案。 金属层包括Ti，TiN，W，WN，Ru，Pt，An或它们的混合物。 混合气体包括氧气，臭氧或其混合物。

公开(公告)号：KR100843230B1

公开(公告)日：2008-07-02

申请号：KR1020070005423

申请日：2007-01-17

Applicant: 삼성전자주식회사

Inventor： 이병학 ,  손웅희 ,  박재화 ,  최길현 ,  김병희 ,  박희숙

IPC: H01L21/336

CPC classification number: H01L21/823842 ,  H01L21/28052 ,  H01L21/28247

Abstract: A semiconductor device including a gate electrode having a metal layer and a manufacturing method thereof are provided to reduce contact resistance in a gate line pattern by inserting an ohmic layer between a fist metal layer and a conductive polysilicon layer. A gate insulating layer(110) is formed on a semiconductor substrate(100). A gate including a stacked structure of a first metal layer(120), a first metal silicide layer(124), and a conductive polysilicon layer(130) is formed on the gate insulating layer of the semiconductor substrate. The first metal layer is composed of one element selected from a group including tungsten nitride, molybdenum nitride, tungsten carbon nitride, RuO2, Ni, Ir, and Pt. The first metal silicide layer is composed of one metal silicide selected from a group including tungsten silicide, molybdenum silicide, titanium silicide, tantalum silicide, and cobalt silicide.

Abstract translation: 提供包括具有金属层的栅电极及其制造方法的半导体器件，以通过在第一金属层和导电多晶硅层之间插入欧姆层​​来降低栅极线图案中的接触电阻。 在半导体衬底（100）上形成栅极绝缘层（110）。 在半导体衬底的栅绝缘层上形成包括第一金属层（120），第一金属硅化物层（124）和导电多晶硅层（130）的堆叠结构的栅极。 第一金属层由选自氮化钨，氮化钼，碳氮化钨，RuO 2，Ni，Ir和Pt中的一种元素构成。 第一金属硅化物层由选自包括硅化钨，硅化钼，硅化钛，硅化钽和硅化钴的组中的一种金属硅化物组成。

公开(公告)号：KR1020080035919A

公开(公告)日：2008-04-24

申请号：KR1020060102587

申请日：2006-10-20

Applicant: 삼성전자주식회사

Inventor： 박희숙 ,  이병학 ,  차태호 ,  손웅희 ,  이장희 ,  박재화

IPC: H01L27/115

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L29/513 ,  H01L21/28141 ,  H01L21/28202

Abstract: A flash memory device and a method for fabricating the same are provided to prevent oxidation of a sidewall of a metal gate by protecting a side of the metal gate with a low temperature oxide layer. A gate dielectric(120a) is formed on a semiconductor substrate(122a). The gate dielectric traps a carrier tunneled from the semiconductor substrate. The gate dielectric has a first width. A metal electrode(200a) is formed on the gate dielectric. A voltage required for the tunneling is applied to the metal electrode. The metal electrode has a second width smaller than the first width. A sidewall spacer(210a) surrounds a side of the metal electrode. The sidewall spacer prevents oxidization of the metal electrode. The gate dielectric includes silicon oxide(SiOx) formed on the semiconductor substrate, silicon nitride(SiN) formed on the silicon oxide, and aluminum oxide(AlOx) formed on the silicon nitride. The sidewall spacer is a low temperature oxide layer which is formed below the temperature of which the metal electrode is oxidized.

Abstract translation: 提供闪速存储器件及其制造方法，以通过用低温氧化物层保护金属栅极的一侧来防止金属栅极的侧壁的氧化。 栅电介质（120a）形成在半导体衬底（122a）上。 栅极电介质捕获从半导体衬底隧穿的载体。 栅极电介质具有第一宽度。 金属电极（200a）形成在栅极电介质上。 将隧道所需的电压施加到金属电极。 金属电极具有小于第一宽度的第二宽度。 侧壁间隔件（210a）围绕金属电极的一侧。 侧壁间隔物防止金属电极的氧化。 栅电介质包括在半导体衬底上形成的氧化硅（SiOx），在氧化硅上形成的氮化硅（SiN）和在氮化硅上形成的氧化铝（AlOx）。 侧壁间隔物是在金属电极被氧化的温度以下形成的低温氧化物层。