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公开(公告)号：KR1020100008210A
公开(公告)日：2010-01-25
申请号：KR1020080068664
申请日：2008-07-15
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78624 , H01L29/66765 , H01L29/458 , H01L29/78621
Abstract: PURPOSE: A poly-Si thin film transistor and method of manufacturing the same are provided to reduce the cost without the additional ion injection processes and photolithographic process. CONSTITUTION: In order that the gate(112) is covered, the gate insulating layer(114) is formed in the top of the substrate. The active layer(116) is formed on the gate insulating layer. The active layer is composed of the poly-silicon. The first polysilicon layer(117) is respectively formed in both-sided upper side of the active layer. The first polysilicon layer is doped in the low concentration. The second polysilicon layer(118) is respectively formed in the upper side of first polysilicon layers. The second polysilicon layer is doped in the concentration like the first polysilicon layer or the high concentration. Source / drain electrodes(120a,120b) are respectively formed in the upper side of second polysilicon layers.
Abstract translation: 目的：提供多晶硅薄膜晶体管及其制造方法，以降低成本，而不需要额外的离子注入工艺和光刻工艺。 构成：为了使栅极（112）被覆盖，栅极绝缘层（114）形成在衬底的顶部。 有源层（116）形成在栅极绝缘层上。 有源层由多晶硅组成。 第一多晶硅层（117）分别形成在有源层的双面上侧。 第一多晶硅层以低浓度掺杂。 第二多晶硅层（118）分别形成在第一多晶硅层的上侧。 第二多晶硅层以类似于第一多晶硅层或高浓度的浓度掺杂。 源极/漏极（120a，120b）分别形成在第二多晶硅层的上侧。
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公开(公告)号：KR1020090052228A
公开(公告)日：2009-05-25
申请号：KR1020070118827
申请日：2007-11-20
Applicant: 삼성전자주식회사
IPC: H01L21/20 , H01L29/786 , B82Y40/00
CPC classification number: H01L21/02675 , H01L21/02532 , H01L29/66765 , Y10S977/762 , Y10S977/778 , H01L21/02672
Abstract: 다결정 실리콘 박막 및 이를 적용하는 박막 트랜지스터의 제조방법이 개시된다. 개시된 다결정 실리콘 박막의 제조방법은 기판 상에 비정질 실리콘으로 활성층을 형성하는 단계; 상기 활성층에 금 나노로드를 도포하는 단계; 상기 금 나노로드에 적외선 영역의 광을 조사하여 상기 활성층을 결정화 시키는 단계;를 포함한다.
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公开(公告)号：KR1020080102029A
公开(公告)日：2008-11-24
申请号：KR1020070048310
申请日：2007-05-17
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/7869 , H01L29/78696
Abstract: A thin film transistor of ZnO system and a manufacturing method thereof are provided to suppress the damage of the channel layer due to plasma by controlling the concentration of carrier. A thin film transistor of ZnO system comprises the substrate(10); the ZnO system channel layer(22) formed on the substrate; the gate(20) arranged between the substrate and the channel layer; the gate isolation layer(21) prepared between the channel layer and the gate; the source and the drain electrodes(23a,24a) prepared at both sides of the channel; the passivation layer(24) covering the channel layer, the source and drain electrodes. The channel layer includes chloride.
Abstract translation: 提供ZnO系的薄膜晶体管及其制造方法，通过控制载流子的浓度来抑制由于等离子体引起的沟道层的损伤。 ZnO系薄膜晶体管包括衬底（10）; 所述ZnO系沟道层（22）形成在所述基板上; 所述栅极（20）布置在所述基板和所述沟道层之间; 所述栅极隔离层（21）在所述沟道层和所述栅极之间制备; 在通道的两侧准备的源电极和漏电极（23a，24a）; 所述钝化层（24）覆盖所述沟道层，所述源极和漏极。 通道层包括氯化物。
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公开(公告)号：KR1020080056581A
公开(公告)日：2008-06-23
申请号：KR1020060129656
申请日：2006-12-18
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78621 , H01L29/66757
Abstract: A method for fabricating a thin film transistor is provided to reduce off-current by fabricating a thin film transistor having an LDD(lightly doped drain) region between a source/drain region and a channel region. An amorphous silicon layer is formed on a substrate(10). The amorphous silicon layer is crystallized to form a polysilicon layer. An insulation layer is formed on the polysilicon layer. A mask structure is formed on the insulation layer to mask a partial region of the polysilicon layer, including a gate mask and a photoresist layer that are sequentially stacked. Impurities of a first density are implanted into one and the other ends of the polysilicon layer not covered with the mask structure by an ion beam implantation method to form a source region(14S), a drain region(14D) and a channel region(14C) between the source and drain regions in the polysilicon layer. An ion beam is irradiated to the photoresist layer to shrink the photoresist layer so that one and the other ends of the gate mask are protruded. By using the shrunk photoresist layer as an etch mask, the gate mask and the insulation layer are etched by the same width as the shrunk photoresist layer to form a gate electrode(22a) and a gate insulation layer(16a). Impurities of a second density lower than the first density are implanted into one and the other ends of the channel region exposed to a gap between the gate insulation layer and the source/drain region to form an LDD region.
Abstract translation: 提供一种制造薄膜晶体管的方法，通过制造在源极/漏极区域和沟道区域之间具有LDD（轻掺杂漏极）区域的薄膜晶体管来减少截止电流。 在基板（10）上形成非晶硅层。 非晶硅层被结晶以形成多晶硅层。 在多晶硅层上形成绝缘层。 在绝缘层上形成掩模结构，以掩蔽多晶硅层的部分区域，包括顺序层叠的栅极掩模和光致抗蚀剂层。 通过离子束注入方法将第一密度的杂质注入未被掩模结构覆盖的多晶硅层的一端和另一端，以形成源极区（14S），漏极区（14D）和沟道区（14C） ）在多晶硅层中的源区和漏区之间。 将离子束照射到光致抗蚀剂层以收缩光致抗蚀剂层，使得栅极掩模的一端和另一端突出。 通过使用收缩的光致抗蚀剂层作为蚀刻掩模，栅极掩模和绝缘层被蚀刻与收缩光致抗蚀剂层相同的宽度，以形成栅电极（22a）和栅极绝缘层（16a）。 将低于第一密度的第二密度的杂质注入暴露于栅极绝缘层和源极/漏极区之间的间隙的沟道区的一端和另一端，以形成LDD区。
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公开(公告)号：KR1020070115482A
公开(公告)日：2007-12-06
申请号：KR1020060049993
申请日：2006-06-02
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78603 , H01L29/78645 , H01L29/78621
Abstract: A thin film transistor formed on a flexible substrate and a manufacturing method thereof are provided to form uniformly offset regions into each device respectively by forming the offset region between dual gates, even if a mis-alignment exists. A polysilicon layer(44) including a source and a drain regions is formed on a flexible substrate(40). A gate stack(S) is formed on a channel region of the polysilicon layer. The gate stack comprises a first gate stack(S1) and a second gate stack(S2), and an offset region is exposed between the first and the second gate stacks.
Abstract translation: 形成在柔性基板上的薄膜晶体管及其制造方法分别通过在双栅极之间形成偏移区域来分别形成均匀的偏移区域，即使存在错误对准。 在柔性基板（40）上形成包括源区和漏区的多晶硅层（44）。 在多晶硅层的沟道区上形成栅叠层（S）。 栅极堆叠包括第一栅极堆叠（S1）和第二栅极堆叠（S2），并且偏移区域暴露在第一和第二栅极堆叠之间。
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Patent Agency Ranking
公开(公告)号：KR1020070074748A
公开(公告)日：2007-07-18
申请号：KR1020060002687
申请日：2006-01-10
Applicant: 삼성전자주식회사
IPC: H01L29/786 , H05B33/00
CPC classification number: H01L29/78645 , H01L27/1288 , H01L27/3244 , H01L29/78624 , H01L29/78696 , H01L27/1214
Abstract: A transistor is provided to reduce fabricating cost of a transistor and a display using the transistor by enabling formation of an offset structure without using a mask. Two polycrystalline silicon layers(10a) are disposed in parallel with each other, having doped high-conductive regions at their both ends and a channel region between the two high-conductive regions. A gate(12) is extended in a direction crossing the two polycrystalline silicon layers. A gate insulation layer is interposed between the gate and the polycrystalline silicon layers. Low-conductive regions(10e) are formed between the channel region of polycrystalline silicon and the high-conductive region, confronting each other and adjoining the edge of one side of the gate. Impurities having a low density can be doped into the low-conductive region as compared with the high-conductive region.
Abstract translation: 提供晶体管以通过在不使用掩模的情况下形成偏移结构来降低晶体管和使用晶体管的显示器的制造成本。 两个多晶硅层（10a）彼此平行地设置，在其两端具有掺杂的高导电区域和两个高导电区域之间的沟道区域。 栅极（12）沿与两个多晶硅层交叉的方向延伸。 栅极绝缘层介于栅极和多晶硅层之间。 低导电区域（10e）形成在多晶硅的沟道区域和相互面对并邻接栅极一侧边缘的高导电区域之间。 与高导电区域相比，可以将具有低密度的杂质掺杂到低导电区域中。
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公开(公告)号：KR100695154B1
公开(公告)日：2007-03-14
申请号：KR1020050052725
申请日：2005-06-18
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/78603 , H01L29/66757
Abstract: 개시된 실리콘 박막 트랜지스터는: 기판의 양면에 버퍼층이 형성되고 일측의 버퍼층에 실리콘 채널이 형성된다. 실리콘 채널 위에는 게이트 절연층가 형성되고 게이트 절연층 위에는 게이트가 마련된다. 기판 양면에 형성되는 버퍼층에 의해 기판의 휨이 방지되고 따라서 양질의 동작 성능을 갖는다.
다결정, 실리콘, 버퍼층, 스트레스, 휨-
公开(公告)号：KR1020060121514A
公开(公告)日：2006-11-29
申请号：KR1020050043743
申请日：2005-05-24
Applicant: 삼성전자주식회사
CPC classification number: H01L27/1229 , H01L27/1214 , H01L27/1274 , H01L27/3244 , H01L29/04
Abstract: An organic light emitting display and a method for fabricating the same are provided to use a plastic or a glass as a substrate material by not adopting an LDD(Lightly Doped Drain) structure to reduce an off current. In an organic light emitting display, a plurality of pixels is arranged at a substrate(11) like a matrix shape and includes a switching transistor(Qs), a driving transistor(Qd), and an OLED(Organic Light Emitting Diode). And, the switching transistor(Qs) includes a silicon channel having a lower mobility than the driving transistor(Qd).
Abstract translation: 提供一种有机发光显示器及其制造方法，通过不采用LDD（轻掺杂漏极）结构来降低截止电流，使用塑料或玻璃作为基板材料。 在有机发光显示器中，多个像素被布置在像矩阵形状的基板（11）处，并且包括开关晶体管（Qs），驱动晶体管（Qd）和OLED（有机发光二极管）。 并且，开关晶体管（Qs）包括具有比驱动晶体管（Qd）低的迁移率的硅沟道。
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公开(公告)号：KR100624430B1
公开(公告)日：2006-09-19
申请号：KR1020040056815
申请日：2004-07-21
Applicant: 삼성전자주식회사
IPC: H01L29/786
Abstract: 양질의 다결정 실리콘 TFT의 제조제조방법에 관해 개시된다. 본 발명에 따른 다결정 실리콘 TFT의 제조방법은:
게이트 위에 게이트 절연물질층과 비정질 실리콘층을 ICP-CVD(Inductively Coupled Plasma Chemical Vapor Deposition )에 의해 연속 형성하는 단계; 상기 비정질 실리콘을 열처리하여 다결정 실리콘을 형성하는 단계;를 포함하고,
상기 게이트절연물질층을 형성하기 위하여 SiH
4 /O
2 /Ar 을 1:25:50 sccm 으로 공급하고, 파워는 1000W, 압력은 15mTorr로 조절한다.
본 발명은 하나의 챔버 내에서 게이트 절연층과 실리콘층이 연속 증착되기 때문에 게이트 절연층과 실리콘 층간의 계면 특성의 악화를 방지할 수 있다.
다결정, 바텀, 게이트, TFT-
公开(公告)号：KR1020060079958A
公开(公告)日：2006-07-07
申请号：KR1020050000381
申请日：2005-01-04
Applicant: 삼성전자주식회사
IPC: H01L29/786
CPC classification number: H01L29/66757 , H01L29/4908
Abstract: 개시된 실리콘 박막트랜지스터는: 기판에 형성되는 실리콘 채널과; 상기 실리콘 채널 위에 형성되는 게이트 절연층과; 상기 게이트 절연층 위에 마련되는 게이트를; 구비하고, 상기 게이트 절연층은 HfOx
박막을 포함하는 구조를 가진다. 이러한 박막트랜지스터는 낮은 전류누설특성을 가진다.
다결정, 실리콘, 게이트 절연층, HfOx, HfO2
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