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公开(公告)号：KR101020513B1
公开(公告)日：2011-03-09
申请号：KR1020080087332
申请日：2008-09-04
Applicant: 한국전자통신연구원
CPC classification number: H03L7/095
Abstract: 본 발명에 따른 락 검출 회로는 2개의 지연 소자, 4개의 플립플롭, 2개의 논리 게이트로 구현이 가능하면서 PLL 회로의 락 상태를 정확하게 검출할 수 있다. 따라서, 락 검출 회로를 간단한 구조로 구현할 수 있으므로, 이에 따라 락 검출 회로의 소형화를 도모할 수 있으며 소비전력을 감소시킬 수 있다. 또한, 본 발명에 따른 락 검출 방법에 의하면, 락 상태를 검출하는 과정이 간단해지므로 빠른 시간내에 락 상태를 검출할 수 있다.
PLL(위상고정루프), 락(lock), 위상 주파수 검출기(PFD)-
公开(公告)号：KR1020110011511A
公开(公告)日：2011-02-08
申请号：KR1020100020194
申请日：2010-03-08
Applicant: 한국전자통신연구원
CPC classification number: H03B5/24 , H03B5/1215 , H03B5/1228 , H03B5/1265 , H03B2200/009
Abstract: PURPOSE: An LC voltage controlled generator is provided to reduce a power value in a specific offset frequency by improving the flicker noise of the LC voltage controlled generator. CONSTITUTION: An LC resonance circuit(210) comprises an inductor connected to a power terminal, a capacitor having a parallel connection with the inductor, and a variable capacitor which is connected in parallel between the inductor and the capacitor. An amplification circuit(220) includes a pair of negative boosting transistors and a pair of switching transistors. The gate node of the switching transistor is connected to a bias voltage through each resistor. A bias voltage supply circuit(230) comprises a current source and a transistor. The gate of the transistor has a constant DC voltage through a current source in the bias voltage supply circuit.
Abstract translation: 目的：提供LC电压控制发生器，通过提高LC电压控制发电机的闪烁噪声来降低特定偏移频率的功率值。 构成：LC谐振电路（210）包括连接到电源端子的电感器，与电感器并联的电容器，以及并联连接在电感器和电容器之间的可变电容器。 放大电路（220）包括一对负升压晶体管和一对开关晶体管。 开关晶体管的栅极节点通过每个电阻器连接到偏置电压。 偏置电压供给电路（230）包括电流源和晶体管。 晶体管的栅极通过偏压电源电路中的电流源具有恒定的直流电压。
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公开(公告)号：KR100925034B1
公开(公告)日：2009-11-03
申请号：KR1020070057601
申请日：2007-06-13
Applicant: 한국전자통신연구원
IPC: H03K19/0175
CPC classification number: H03K19/018528 , H03K19/0948
Abstract: 본 발명은 비동기 디지털 신호레벨 변환회로에 관한 것으로, 제 1 전압레벨의 입력신호를 제 2 전압레벨의 신호로 전압레벨을 변환하는 디지털 신호레벨 변환회로에 있어서, 입력신호의 전압레벨이 변화되는 경우, 입력신호의 빠른 전압레벨 변환을 위해 제 1 전압레벨의 입력신호가 제 2 전압레벨의 신호로 변환되는 제 1, 2 노드를, 전압레벨 변환 과정동안 상기 제 2 전압레벨을 갖는 제 2 전원전압에 연결되도록 함으로써, 신호레벨 변환속도가 개선된 것을 특징으로 한다.
레벨변환, 이중전원전압, CCLC, 변환 속도-
公开(公告)号：KR1020090013312A
公开(公告)日：2009-02-05
申请号：KR1020070077314
申请日：2007-08-01
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/002 , H03M1/44
Abstract: A control method of pipeline analog/digital converter and a pipeline analog/digital converter are provided to minimize sampling mismatch by controlling a sampling point. A pipeline analog/digital converter does not use a shear sample-and-hold amplifier. A first stage of the pipeline analog/digital converter comprises an A/D converter and a residual signal generator. The A/D converter(420) samples the analog input signal and produces first sampling value. The A/D converter amplifies the first sampling value and converses the first sampling value to corresponding digital code. The residual signal generator(410) samples an analog input signal at the same time with the sampling by the A/D converter and produces second sampling value. While the A/D converter amplifies the first sampling value, the residual signal generator holds the second sampling value. The residual signal generator produces the residual signal by using the second sampling value and digital code and delivers the generated residual signal to the second stage.
Abstract translation: 提供管线模拟/数字转换器和流水线模拟/数字转换器的控制方法，以通过控制采样点来最小化采样失配。 管道模拟/数字转换器不使用剪切采样和保持放大器。 管线模拟/数字转换器的第一级包括A / D转换器和残余信号发生器。 A / D转换器（420）对模拟输入信号进行采样并产生第一采样值。 A / D转换器放大第一采样值并将第一采样值转换为相应的数字码。 残余信号发生器（410）通过A / D转换器的采样同时对模拟输入信号进行采样，并产生第二采样值。 当A / D转换器放大第一采样值时，剩余信号发生器保持第二采样值。 剩余信号发生器通过使用第二采样值和数字码产生残余信号，并将产生的残留信号传送到第二级。
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公开(公告)号：KR100874700B1
公开(公告)日：2008-12-18
申请号：KR1020070057137
申请日：2007-06-12
Applicant: 한국전자통신연구원
IPC: H01L29/73
Abstract: A high-speed low-voltage differential signal driving unit using a method for fabricating a bipolar transistor is provided to embody a differential signal driving circuit capable of operating at a high speed by replacing a switching device of a differential signal driving circuit by a bipolar transistor of a field effect transistor. A differential signal driving circuit(420) switches an inputted differential signal to output a common mode voltage through a first output node and a second output node. A common mode feedback circuit(410) supplies predetermined current to the differential signal driving circuit or receives predetermined current from the differential signal driving circuit according to the common mode voltage. The differential signal driving circuit includes a common mode voltage output part for outputting a common mode voltage of the differential signal driving circuit wherein the common mode voltage output part connects the first and second output nodes. The differential signal is inputted through two bipolar transistors. The common mode voltage output part can include first and second resistors between the first and second output nodes wherein the common mode voltage is outputted through an intermediate node that connects the first and second resistors.
Abstract translation: 提供一种使用制造双极晶体管的方法的高速低压差分信号驱动单元，以通过用双极晶体管替换差分信号驱动电路的开关器件来实现能够高速工作的差分信号驱动电路 场效应晶体管。 差分信号驱动电路（420）切换输入的差分信号以通过第一输出节点和第二输出节点输出共模电压。 共模反馈电路（410）根据共模电压向差分信号驱动电路提供预定电流或从差分信号驱动电路接收预定电流。 差分信号驱动电路包括共模电压输出部分，用于输出差分信号驱动电路的共模电压，其中共模电压输出部分连接第一和第二输出节点。 差分信号通过两个双极晶体管输入。 共模电压输出部分可以包括第一和第二输出节点之间的第一和第二电阻器，其中共模电压通过连接第一和第二电阻器的中间节点输出。
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Patent Agency Ranking
公开(公告)号：KR1020080052236A
公开(公告)日：2008-06-11
申请号：KR1020070057137
申请日：2007-06-12
Applicant: 한국전자통신연구원
IPC: H01L29/73
Abstract: A high-speed low-voltage differential signal driving unit using a method for fabricating a bipolar transistor is provided to embody a differential signal driving circuit capable of operating at a high speed by replacing a switching device of a differential signal driving circuit by a bipolar transistor of a field effect transistor. A differential signal driving circuit(420) switches an inputted differential signal to output a common mode voltage through a first output node and a second output node. A common mode feedback circuit(410) supplies predetermined current to the differential signal driving circuit or receives predetermined current from the differential signal driving circuit according to the common mode voltage. The differential signal driving circuit includes a common mode voltage output part for outputting a common mode voltage of the differential signal driving circuit wherein the common mode voltage output part connects the first and second output nodes. The differential signal is inputted through two bipolar transistors. The common mode voltage output part can include first and second resistors between the first and second output nodes wherein the common mode voltage is outputted through an intermediate node that connects the first and second resistors.
Abstract translation: 提供一种使用制造双极晶体管的方法的高速低电压差分信号驱动单元，以实现能够通过双极晶体管代替差分信号驱动电路的开关器件而能够高速工作的差分信号驱动电路 的场效应晶体管。 差分信号驱动电路（420）通过第一输出节点和第二输出节点切换输入的差分信号以输出共模电压。 共模反馈电路（410）将预定电流提供给差分信号驱动电路，或者根据共模电压从差分信号驱动电路接收预定电流。 差分信号驱动电路包括用于输出差分信号驱动电路的共模电压的共模电压输出部分，其中共模电压输出部分连接第一和第二输出节点。 差分信号通过两个双极晶体管输入。 共模电压输出部分可以包括第一和第二输出节点之间的第一和第二电阻器，其中共模电压通过连接第一和第二电阻器的中间节点输出。
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公开(公告)号：KR1020080024676A
公开(公告)日：2008-03-19
申请号：KR1020060089083
申请日：2006-09-14
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1225 , H03M1/168
Abstract: A multi-bit pipeline analog-to-digital converter is provided to decrease a chip size by arranging amplifiers between an SHA(Sampling and Holding Agent) and an MDAC of a first stage. A multi-bit pipeline analog-to-digital converter includes an SHA(10), an N-bit flash ADC(Analog Digital Converter)(20), an N-bit MDAC(30), and a 3-stage amplifier(AMP1). The SHA samples and holds an input analog voltage and removes a sampling error from an input voltage. The N-bit flash ADCs of first to K-th stages receive an analog signal and convert the analog signal to a digital signal. The N-bit MDACs of first to K-th stages convert a difference between an output digital signal from the N-bit flash ADC and the output signal from a previous stage into an analog signal and outputs the analog signal. The 3-stage amplifier is connected to the N-bit MDAC(Multiplying Digital to Analog Converter) output of the first stage at a first clock. At a second clock, the 3-stage amplifier is connected to an output of the SHA.
Abstract translation: 提供了一种多位流水线模数转换器，通过在SHA（采样和保持代理）与第一级的MDAC之间布置放大器来减小芯片尺寸。 多位流水线模数转换器包括SHA（10），N位闪存ADC（模拟数字转换器）（20），N位MDAC（30）和3级放大器（AMP1 ）。 SHA采样并保持输入模拟电压，并从输入电压中消除采样误差。 第一至第K级的N位闪存ADC接收模拟信号，并将模拟信号转换为数字信号。 第一至第K级的N位MDAC将来自N位闪存ADC的输出数字信号与来自前一级的输出信号之间的差转换为模拟信号，并输出模拟信号。 3级放大器在第一时钟连接到第一级的N位MDAC（乘法数模转换器）输出。 在第二个时钟，3级放大器连接到SHA的输出。
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公开(公告)号：KR100746563B1
公开(公告)日：2007-08-08
申请号：KR1020060046037
申请日：2006-05-23
Applicant: 한국전자통신연구원
IPC: H03M1/66
Abstract: 본 발명은 디지털 신호를 아날로그 신호로 바꾸어주는 디지털-아날로그 변환기에 관한 것이다. 본 발명의 디지털-아날로그 변환기는 디지털 입력으로부터 전류원을 선택하기 위한 디코더와, 전류원의 전류스위치를 구동하는 전류스위치 드라이버, 및 디코더와 전류스위치 드라이버 사이에 위치하며 매 클럭마다 디코더의 출력과 전류스위치 드라이버의 입력의 연결관계를 임의로 재설정하는 임의선택 스위치를 포함한다. 본 발명에 의하면, 매 클럭신호마다 선택되는 전류원들을 바꾸어줌으로써 전류원들의 공간적인 배치에 따른 디지털-아날로그 변환기의 비선형성을 평균적으로 보상하여 디지털-아날로그 변환기의 선형성을 높일 수 있다.
디지털-아날로그 변환기, Digital-to-Analog Converter, DAC-
公开(公告)号：KR1020070059844A
公开(公告)日：2007-06-12
申请号：KR1020060046037
申请日：2006-05-23
Applicant: 한국전자통신연구원
IPC: H03M1/66
CPC classification number: H03M1/66 , H03M1/0621 , H03M1/1023 , H03M2201/63 , H03M2201/6372
Abstract: A dynamic linearization digital-to-analog converter is provided to obtain high dynamic linearity by dynamically compensating deterioration of linearity due to mismatch caused by spatial arrangement of unit current sources. A dynamic linearization digital-to-analog converter includes a decoder(12), a current switch driver(14), and a random selecting switch(13). The decoder(12) selects a current source(15) from a digital input. The current switch driver(14) drives a current switch of the current source(15). The random selecting switch(13) is located between the decoder(12) and the current switch driver(14), and resets connection between an output of the decoder(12) and an input of the current switch driver(14) randomly every clock.
Abstract translation: 提供动态线性化数模转换器，以通过动态补偿由于单位电流源的空间布置引起的失配引起的线性劣化，以获得高动态线性度。 动态线性化数模转换器包括解码器（12），电流开关驱动器（14）和随机选择开关（13）。 解码器（12）从数字输入端选择电流源（15）。 当前的开关驱动器（14）驱动电流源（15）的电流开关。 随机选择开关（13）位于解码器（12）和电流开关驱动器（14）之间，并且每时钟随机地重置解码器（12）的输出和当前开关驱动器（14）的输入端之间的连接 。
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公开(公告)号：KR100673483B1
公开(公告)日：2007-01-24
申请号：KR1020040097479
申请日：2004-11-25
Applicant: 한국전자통신연구원
CPC classification number: H03M1/0604 , H03M1/1215 , H03M1/167 , H03M1/804
Abstract: 본 발명의 다중 경로 아날로그 디지털 변환기는 별도의 오프셋 보정회로의 추가 없이, 우수한 오프셋 제거를 달성한다.
다중 파이프 라인 아날로그 디지털 변환기는 아날로그 디지털 변환기 및 멀티 플라잉 디지털 아날로그 변환기를 포함하며, 상기 멀티 플라잉 디지털 아날로그 변환기는 샘플링 구간 동안 증폭기의 동작을 최적화 하거나, 증폭기의 보상 커패시터의 용량을 증가시키거나, 증폭기에 인가되는 바이어스 전류를 조절함으로써 오프셋을 효과적으로 제거할 수 있다.
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