公开(公告)号：KR1020030062076A

公开(公告)日：2003-07-23

申请号：KR1020020002497

申请日：2002-01-16

Applicant: 한국전자통신연구원

Inventor： 장문규 ,  조원주 ,  이성재 ,  박경완

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

Abstract: PURPOSE: A method for fabricating a nano transistor is provided to arbitrarily control a threshold voltage of a n-type metal oxide semiconductor(NMOS) transistor and a p-type metal oxide semiconductor(PMOS) transistor by applying a voltage to a silicon-on-insulator(SOI) substrate. CONSTITUTION: The first impurity ions are implanted into a predetermined region of the SOI substrate having a silicon substrate(21), a buried oxide layer and a silicon layer to form the first well in a predetermined region on the silicon substrate. The second impurity ion implantation process is performed on another region of the SOI substrate to form the second well in another region on the silicon substrate. After a predetermined region of the silicon layer is removed, the first and second gate electrodes having a gate insulation layer(28) and a conductive layer are formed in a predetermined region on the remaining silicon layer. The first and second sources/drains are formed in a predetermined region on the remaining silicon layer. An insulation layer(33) is formed and partially etched to form the first contact hole exposing the first and second wells. A predetermined region of the insulation layer is etched to form the second contact hole exposing the first gate electrode, the second gate electrode and the source/drain. A metal layer is formed to fill the first and second contact holes and is patterned to form a metal interconnection(35).

Abstract translation: 目的：提供一种制造纳米晶体管的方法，通过向硅上施加电压来任意地控制n型金属氧化物半导体（NMOS）晶体管和p型金属氧化物半导体（PMOS）晶体管的阈值电压 - 绝缘体（SOI）衬底。 构成：将第一杂质离子注入到具有硅衬底（21），掩埋氧化物层和硅层的SOI衬底的预定区域中，以在硅衬底上的预定区域中形成第一阱。 在SOI衬底的另一区域上执行第二杂质离子注入工艺以在硅衬底上的另一区域中形成第二阱。 在除去硅层的预定区域之后，在剩余硅层上的预定区域中形成具有栅极绝缘层（28）和导电层的第一和第二栅电极。 第一和第二源极/漏极形成在剩余硅层上的预定区域中。 形成绝缘层（33）并部分蚀刻以形成暴露第一和第二阱的第一接触孔。 蚀刻绝缘层的预定区域以形成暴露第一栅极电极，第二栅极电极和源极/漏极的第二接触孔。 形成金属层以填充第一和第二接触孔并被图案化以形成金属互连（35）。

公开(公告)号：KR1020030034920A

公开(公告)日：2003-05-09

申请号：KR1020010066742

申请日：2001-10-29

Applicant: 한국전자통신연구원

Inventor： 이성재 ,  조원주 ,  박경완

IPC: H01L21/265

CPC classification number: H01L29/66598 ,  H01L21/2255 ,  H01L21/3115 ,  H01L21/31155 ,  H01L29/6659

Abstract: PURPOSE: A method for fabricating an integrated circuit with a shallow junction is provided to prevent the crystal structure of a substrate from being damaged by not directly implanting impurity ions into the substrate while precisely controlling the density of the impurities through a plasma ion implantation method. CONSTITUTION: A diffusion blocking layer pattern(12) is formed on the semiconductor substrate(10). An impurity-containing spin-on-glass(SOG) layer is formed on the semiconductor substrate having the diffusion blocking layer pattern. The impurity ions are additionally implanted into the SOG layer through a plasma ion implantation method to increase the impurity density of the SOG layer. The impurities included in the SOG layer having the increased impurity density are diffused to the semiconductor substrate to form a shallow junction(16a,16b) through a solid phase diffusion method.

Abstract translation: 目的：提供一种用于制造具有浅结的集成电路的方法，以通过不通过等离子体离子注入方法精确地控制杂质的密度而将杂质离子直接注入到衬底中来防止衬底的晶体结构受损。 构成：在半导体衬底（10）上形成扩散阻挡层图案（12）。 在具有扩散阻挡层图案的半导体衬底上形成含杂质的旋涂玻璃（SOG）层。 通过等离子体离子注入法将杂质离子另外注入SOG层，以增加SOG层的杂质浓度。 包含在具有增加的杂质浓度的SOG层中的杂质通过固相扩散法扩散到半导体衬底以形成浅结（16a，16b）。

公开(公告)号：KR1020020076386A

公开(公告)日：2002-10-11

申请号：KR1020010016190

申请日：2001-03-28

Applicant: 한국전자통신연구원

Inventor： 조원주 ,  이성재 ,  박경완

IPC: H01L29/78

CPC classification number: H01L29/78642 ,  H01L27/1203 ,  Y10S977/712 ,  Y10S977/721 ,  Y10S977/723 ,  Y10S977/887

Abstract: PURPOSE: An ultra small size vertical MOSFET device and fabrication method of the MOSFET device is provided to be capable of forming an ultra-fine vertical channel by using an SOI(Silicon On Insulator) substrate without using a lithographic processing. CONSTITUTION: A first silicon conductive layer(31) is formed by doping heavily doped dopants into an SOI substrate. After sequentially forming a lightly doped silicon layer and a heavily doped second silicon conductive layer on the first silicon conductive layer(31), the silicon layer and the second silicon conductive layer are vertically etched. After forming a gate oxide(70) on the resultant structure, the heavily doped impurities in the first and second silicon conductive layers are diffused to the silicon layer, thereby simultaneously forming a source (140), a channel(41) and a drain(90) having a vertical structure. Then, a gate electrode(101) is formed at both sidewalls of the vertical structure.

Abstract translation: 目的：提供超小尺寸垂直MOSFET器件和MOSFET器件的制造方法，以便能够通过使用SOI（绝缘体上硅）衬底形成超细垂直沟道，而不使用光刻处理。 构成：通过将重掺杂的掺杂剂掺杂到SOI衬底中而形成第一硅导电层（31）。 在第一硅导电层（31）上顺序地形成轻掺杂硅层和重掺杂的第二硅导电层之后，对硅层和第二硅导电层进行垂直蚀刻。 在所得结构上形成栅极氧化物（70）之后，第一和第二硅导电层中的重掺杂杂质扩散到硅层，从而同时形成源极（140），沟道（41）和漏极（ 90）具有垂直结构。 然后，在垂直结构的两个侧壁处形成栅电极（101）。

公开(公告)号：KR100349662B1

公开(公告)日：2002-08-22

申请号：KR1019990057255

申请日：1999-12-13

Applicant: 한국전자통신연구원

Inventor： 김성복 ,  노정래 ,  박경완

IPC: H01S5/32

Abstract: 본발명은산화알루미늄층을이용한전류차단구조와그를이용한양자점레이저다이오드의제조방법에관한것으로, 이를위한본 발명의전류차단구조형성방법은제1 도전형기판상에제1 도전형제1클래딩층을형성하는제 1 단계, 상기제1클래딩층상부에자발적으로양자점활성층을성장시키는제 2 단계, 상기양자점활성층을산화마스크로이용하여상기제1클래딩층을산화시켜전류차단층을형성하는제 3 단계, 상기전류차단층을포함한양자점활성층상에제2 도전형제2클래딩층을형성하는제 4 단계, 상기제2 도전형제2클래딩층상에제2 도전형캡층을형성하는제 5 단계를포함하여이루어진다.

公开(公告)号：KR100325689B1

公开(公告)日：2002-02-25

申请号：KR1019990054157

申请日：1999-12-01

Applicant: 한국전자통신연구원

Inventor： 신민철 ,  이성재 ,  박경완

IPC: G11C11/404

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/7888 ,  Y10S977/937

Abstract: 본발명은상관된단전자관통(Correlated Single Electron Tunneling) 현상을보이는두 개이상의양자점관통접합배열을적절히결합하고, 이때 유도되는전자 - 홀쌍(Electron - Hole Pair)의쿨롱가로막기(Coulomb Blockade) 현상을이용한메모리소자를제공하는데그 목적이있다. 본발명에따르면, 전자 - 홀쌍에의한쿨롱가로막기현상(Coulomb Blockade Phenomena)을이용하고적어도두 개의양자점관통접합배열을포함하는단전자메모리소자에있어서, 상기양자점관통접합배열은각각적어도두개의관통접합으로구성되어있으며, 서로평행하게배치되어전기적으로기설정된결합력보다크게끔결합되어있고, 결합접합면에서전자의이동이일어나지않도록서로멀리떨어져있으며; 상기양자점관통접합배열중 어느하나는전자 - 홀쌍의개수를변화시킬수 있는게이트전압을인가하기위한게이트전극을포함하고, 상기양자점관통접합배열각각은소오스 - 드레인전압을인가할수 있는소오스및 드레인단자를포함하여이루어진것을특징으로하는단전자메모리소자가제공된다.

公开(公告)号：KR100299664B1

公开(公告)日：2001-10-27

申请号：KR1019970050803

申请日：1997-10-01

Applicant: 한국전자통신연구원

Inventor： 박경완 ,  신민철 ,  오상철 ,  박문호 ,  이성재

IPC: H01L29/737

Abstract: PURPOSE: A method for manufacturing silicon short electron transistor using a secondary electron approaching effect of electron beam picturing process and silicon oxidation process is provided to easily manufacture a silicon short electron transistor by using a secondary electron approaching effect of an electron beam picturing process to form a smaller quantum fine line than a size of the electron beam and by using a silicon oxidation process to form a tunneling junction. CONSTITUTION: An electron beam resist is coated on a silicon substrate. A gate(20), source(10), a quantum dot(40) and a drain(30) are exposed by the electron beam picturing method, wherein any width of space is placed between the source and the quantum dot and between the drain and the quantum dot. A narrower fine lines(50) than a mean line width of the source and the drain are exposed between the source due to the approaching defect of a secondary electron by performing the picturing of the electron beam, quantum dot and the drain. The fine lines have a narrower waist shape. After coating a silicon oxide layer on the pictured portion, the silicon is etched by using the oxide layer as a mask. The fine line is insulated by performing a silicon thermal oxidation process and an insulated tunneling junction is formed between the source and the quantum dot and between the quantum dot and the drain.

公开(公告)号：KR1020010053690A

公开(公告)日：2001-07-02

申请号：KR1019990054157

申请日：1999-12-01

Applicant: 한국전자통신연구원

Inventor： 신민철 ,  이성재 ,  박경완

IPC: G11C11/404

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/7888 ,  Y10S977/937

Abstract: PURPOSE: A single electron memory device using an electron-hole combination is provided, which combines more than two quantum dot tunnel junction arrays properly showing correlated single electron tunneling phenomenon, and uses a Coulomb blockade phenomenon of an electron-hole pair. CONSTITUTION: According to a parallel-coupled single-electron tunnel-junction array, a quantum dot I1 having dual tunnel junction TL1 and TR1 are connected to a source S1 and a drain D1, and a voltage V+ is applied to S1, and a voltage V- is applied to D1. Another dual tunnel junctions TL2 and TR2 are connected by a quantum dot I2, and the quantum dot I2 is connected to a source S2 and a drain D2, and S2 and D2 are grounded. A junction plane C1 of the quantum dot I1 and I2 is combined strongly and electrically by a capacitance Ca, but the transport of electron through the junction plane is not permitted. A gate electrode G is attached to the quantum dot I2 and a gate voltage Vg is applied to the quantum dot I2. And a capacitance of a junction plane C2 between the quantum dot I2 and the gate electrode G is Cg. Another quantum dot I0 is combined to the quantum dot I1 weakly with a junction plane C0 between them. A source electrode S0 and a drain electrode D0 are attached to the quantum dot I0 by tunnel junctions TL0 and TR0 respectively. The quantum dot I0 is used for measuring a voltage of the quantum dot I1.

Abstract translation: 目的：提供一种使用电子 - 空穴组合的单电子存储器件，其结合了两个以上的量子点隧道结阵列，适当地示出了相关的单电子隧道现象，并且使用电子 - 空穴对的库仑阻塞现象。 构成：根据并联耦合的单电子隧道结阵列，具有双隧道结TL1和TR1的量子点I1连接到源S1和漏极D1，并且将电压V +施加到S1， V-应用于D1。 另一个双隧道结TL2和TR2通过量子点I2连接，量子点I2连接到源S2和漏极D2，S2和D2接地。 量子点I1和I2的结平面C1通过电容Ca强烈地和电连接，但不允许通过结面的电子传输。 栅电极G连接到量子点I2，并且栅极电压Vg施加到量子点I2。 并且量子点I2和栅电极G之间的接面C2的电容为Cg。 另一个量子点I0与它们之间的结平面C0微弱地组合到量子点I1。 源电极S0和漏电极D0分别通过隧道结TL0和TR0连接到量子点I0。 量子点I0用于测量量子点I1的电压。

公开(公告)号：KR1020010017268A

公开(公告)日：2001-03-05

申请号：KR1019990032698

申请日：1999-08-10

Applicant: 한국전자통신연구원

Inventor： 박문호 ,  박경완 ,  이성재

IPC: H01L29/786 ,  B82Y40/00

Abstract: PURPOSE: A method for manufacturing a multiple-junction single electron transistor by depositing a thin film is provided to easily form a quantum dot with a metal cluster by a well-controlled metal deposition. CONSTITUTION: An active region pattern composed of a silicon oxide layer is formed on the silicon oxide layer buried on a substrate and on a separation by implanted oxygen(SIMOS) substrate on which a silicon layer is deposited. The buried silicon oxide layer is exposed by a gate contact pattern, and a metal layer is deposited to form a gate contact(21). An ion implantation process for a source/drain channel region is carried out. The active region pattern is split up into two channel patterns whose vertexes face each other by two triangular patterns whose vertexes vertically face each other. The exposed silicon layer is removed, and a side gate(41) is formed on the buried silicon oxide layer. Source and drain contacts(51,52) including an outer portion of the two channel patterns are formed. An aluminum quantum dot pattern is formed between a vertex of the two channel patterns and the side gate. An aluminum thin film having a thickness of several nanometer is deposited to form an aluminum quantum dot(61) composed of an aluminum cluster having a size of several nanometer.

Abstract translation: 目的：提供通过沉积薄膜制造多结单电子晶体管的方法，以通过良好控制的金属沉积容易地形成具有金属簇的量子点。 构成：在掩埋在基板上的氧化硅层上和在其上沉积硅层的注入氧（SIMOS）衬底的分离上形成由氧化硅层构成的有源区域图案。 埋置的氧化硅层通过栅极接触图案曝光，并且沉积金属层以形成栅极接触（21）。 进行源极/漏极沟道区域的离子注入工艺。 有源区域图案被分成两个通道图案，其顶点通过两个三角形图案彼此面对，顶点垂直面对彼此。 去除暴露的硅层，并且在掩埋氧化硅层上形成侧栅极（41）。 形成包括两个通道图案的外部部分的源极和漏极接触（51,52）。 在两个通道图案的顶点和侧门之间形成铝量子点图案。 沉积具有几纳米厚度的铝薄膜以形成由具有几纳米尺寸的铝簇组成的铝量子点（61）。

公开(公告)号：KR100276695B1

公开(公告)日：2001-03-02

申请号：KR1019980052020

申请日：1998-11-30

Applicant: 한국전자통신연구원

Inventor： 박경완 ,  이성재 ,  신민철 ,  박문호

IPC: H01L21/335

Abstract: 본 발명은 전계 효과 트랜지스터의 폴리실리콘 게이트 형성 방법에 관한 것이다.
본 발명에서는 리소그라피 공정에 의하여 전도 채널에 수직으로 폴리실리콘 게이트를 형성하며, 폴리실리콘 게이트의 측면 산화 공정과 식각 공정을 이용하여 게이트의 길이를 리소그라피 공정에 의하여 정해진 선폭 미만으로 줄인다. 이에 따라 전계 효과 트랜지스터의 소오스와 드레인 간의 길이도 줄일 수 있다.
본 발명의 방법을 이용하여 전계 효과 트랜지스터의 게이트 길이를 극한적으로 줄임으로써, 이에 따르는 양자 효과의 전자 소자를 제작할 수 있다.

公开(公告)号：KR1020000037777A

公开(公告)日：2000-07-05

申请号：KR1019980052526

申请日：1998-12-02

Applicant: 한국전자통신연구원

Inventor： 김성복 ,  노정래 ,  박경완

IPC: H01L21/00

Abstract: PURPOSE: A method for manufacturing a quantum wire is provided to obtain a quantum wire which has a better physical characteristics than a quantum well device. CONSTITUTION: A photosensitive layer is coated on an N-type semiconductor material, and then the photosensitive layer is patterned. The N-type semiconductor material is etched to form a V-shaped substrate. Then, the photosensitive pattern is removed. The V-shaped substrate is loaded on depositing equipment. A well layer that has a thickness, which is equal to the width of the upper surface of the V-shaped recess, is formed. A P-type semiconductor layer is formed on the above-mentioned structure.

Abstract translation: 目的：提供量子线的制造方法，以获得具有比量子阱器件更好的物理特性的量子线。 构成：将感光层涂覆在N型半导体材料上，然后对感光层进行图案化。 蚀刻N型半导体材料以形成V形基板。 然后，去除感光图案。 V形基板装载在沉积设备上。 形成具有与V形凹部的上表面的宽度相等的厚度的阱层。 在上述结构中形成P型半导体层。